A band-gap voltage reference for interface circuit of microsensor

A high performance CMOS band-gap voltage reference circuit that can be used in interface integrated circuit of microsensor and compatible with 0. 6 μm ( double poly) mix process is proposed in this paper. The circuit can be employed in the range of 1. 8 - 8 V and carry out the first-order PTAT ( proportional to absolute temperature) temperature compensation. Through using a two-stage op-amp with a NMOS input pair as a negative feedback op-amp,the PSRR ( power supply rejection ratio) of the entire circuit is increased,and the temperature coefficient of reference voltage is decreased. Results from HSPICE simulation show that the PSRR is - 72. 76 dB in the condition of low-frequency,the temperature coefficient is 2. 4 × 10 -6 in the temperature range from - 10 ℃ to 90 ℃ and the power dissipation is only 14 μW when the supply voltage is 1. 8 V.

High-PSRR High-Order Curvature-Compensated CMOS Bandgap Voltage Reference

A high-PSRR high-order curvature-compensated CMOS bandgap voltage reference( BGR),which has the performances of high power supply rejection ratio( PSRR) and low temperature coefficient,is designed in SMIC 0. 18 μm CMOS process. Compared to the conventional curvature-compensated BGR which adopted a piecewise-linear current,the temperature characterize of the proposed BGR is effectively improved by adopting two kinds of current including a piecewise-linear current and a current proportional 1. 5 party to the absolute temperature T. By adopting a low dropout( LDO) regulator whose output voltage is the operating supply voltage of the proposed BGR core circuit instead of power supply voltage VDD,the proposed BGR with LDO regulator achieves a well PSRR performance than the BGR without LDO regulator. Simulation results show that the proposed BGR with LDO regulator achieves a temperature coefficient of 2. 1 × 10-6/ ℃ with a 1. 8 V power supply voltage and a line regulation of 4. 9 μV / V at 27 ℃. The proposed BGR with LDO regulator at 10 Hz,100 Hz,1 k Hz,10 k Hz and 100 k Hz have the PSRR of- 106. 388,- 106. 388,- 106. 38,- 105. 93 and-88. 67 d B respectively.

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/°C with tempera- ture range from -40 °C to 85 °C, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56 dB at 10 MHz.

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient( TC) bandgap reference( BGR) with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio( PSRR) of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^(-6)/℃-9. 56 × 10^(-6)/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^(-6)/℃.

Novel High PSRR Current Reference Based on Subthreshold MOSFETs

This paper takes full advantages of the I-V transcon- ductance characteristics of metal-oxide semiconductor field effect transistor (MOSFET) operating in the subthreshold region and the enhancement pre-regulator technique with the high gain negative feedback loop. The proposed reference circuit, designed with the SMIC 0.18 μm standard complementary metal-oxide semiconduc- tor (CMOS) logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient (TC) of 2.5×10-4 μA /℃ in the temperature range of -40 to 150 ℃ at 1.5 V supply voltage, and also achieves a best PSRR over a broad fre- quency. The PSRR is about -126 dB at DC frequency and remains -92 dB at the frequency higher 100 MHz. Moreover the proposed reference circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.

Adaptive Reference Power Based Voltage Droop Control for VSC-MTDC Systems

Featuring low communication requirements and high reliability,the voltage droop control method is widely adopted in the voltage source converter based multi-terminal direct current(VSC-MTDC)system for autonomous DC voltage regulation and power-sharing.However,the traditional voltage droop control method with fixed droop gain is criticized for over-limit DC voltage deviation in case of large power disturbances,which can threaten stable operation of the entire VSCMTDC system.To tackle this problem,this paper proposes an adaptive reference power based voltage droop control method,which changes the reference power to compensate the power deviation for droop-controlled voltage source converters(VSCs).Besides retaining the merits of the traditional voltage droop control method,both DC voltage deviation reduction and power distribution improvement can be achieved by utilizing local information and a specific control factor in the proposed method.Basic principles and key features of the proposed method are described.Detailed analyses on the effects of the control factor on DC voltage deviation and imbalanced power-sharing are discussed,and the selection principle of the control factor is proposed.Finally,the effectiveness of the proposed method is validated by the simulations on a five-terminal VSC based high-voltage direct current(VSC-HVDC)system.

Analysis of Light Load Efficiency Characteristics of a Dual Active Bridge Converter Using Wide Band-Gap Devices

In this paper, the zero voltage switching (ZVS) region of a dual active bridge (DAB) converter with wide band-gap (WBG) power semiconductor device is analyzed. The ZVS region of a DAB converter varies depending on output power and voltage ratio. The DAB converters operate with hard switching at light loads, it is difficult to achieve high efficiency. Fortunately, WBG power semiconductor devices have excellent hard switching characteristics and can increase efficiency compared to silicon (Si) devices. In particular, WBG devices can achieve ZVS at low load currents due to their low parasitic output capacitance (Co,tr) characteristics. Therefore, in this paper, the ZVS operating resion is analyzed based on the characteristics of Si, silicon carbide (SiC) and gallium nitride (GaN). Power semiconductor devices. WBG devices with low Co,tr operate at ZVS at lower load currents compared to Si devices. To verify this, experiments are conducted and the results are analyzed using a 3 kW DAB converter. For Si devices, ZVS is achieved above 1.4 kW. For WBG devices, ZVS is achieved at 700 W. Due to the ZVS conditions depending on the switching device, the DAB converter using Si devices achieves a power conversion efficiency of 91% at 1.1 kW output. On the other hand, in the case of WBG devices, power conversion efficiency of more than 98% is achieved under 11 kW conditions. In conclusion, it is confirmed that the WBG device operates in ZVS at a lower load compared to the Si device, which is advantageous in increasing light load efficiency.

模拟集成电路设计课程实验项目驱动式教学改革

基于高校模拟集成电路设计课程实验项目分散且教学目标不明确,缺乏系统性和工程应用性,提出了项目驱动式教学改革。以与企业合作的工程项目为基础设立实验项目,并分解成由易及难的多个实验题目,分阶段、分步骤完成实验内容,最终完成模拟集成电路设计全流程实验,以“带隙基准电压源芯片全定制设计实验”为例阐述了实施步骤。课程实验项目采用驱动式教学加深了学生对课程内容的理解,有助于培养学生扎实的工程实践能力。

附带STATCOM的HVDC系统改进参考电压控制法

在弱交流系统下对于附带有STATCOM的电网换相换流器高压直流输电(Line Commutated Converter based High Voltage Direct Current, LCC-HVDC)系统,存在着LCC逆变站与STATCOM之间耦合导致LCC-HVDC系统的稳定裕度下降问题,这会减弱LCC-HVDC抑制换相失败的能力。此外,HVDC控制环节之中的电压指令电流控制(voltage dependent current order limiter, VDCOL)环节的输出电流指令大幅剧烈波动还有几率会导致HVDC系统在首次换相失败之后发生后续换相失败。针对上述问题提出了一种“改进参考电压”的思想,对STATCOM和VDCOL的参考电压与输入电压分别进行修正。首先在STATCOM原本的参考电压经过一个“虚拟电抗”之后得到一个新的参考电压,通过这个改进参考电压弱化了STATCOM电压外环控制模块与LCC逆变站的耦合,减小了交流系统等效阻抗的大小,提升了系统对干扰的抵抗能力。然后对VDCOL的输入电压进行改进,新的改进输入电压改善了故障后VDCOL输出电流指令的大幅剧烈波动情况。最后通过三个层次的对照试验,验证了所提方法的有效性。

基于光伏动态电流参考值的两级式光伏并网系统低电压穿越控制策略

随着光伏接入容量的不断提升,电网电压跌落时光伏脱网会影响系统稳定运行,因此光伏系统应具备低电压穿越(LVRT)能力。然而,目前常用的两级式光伏并网系统LVRT控制策略存在光伏动态响应慢及控制效果受限于光伏P–U特性曲线的数学模型精度等问题,且未考虑局部阴影条件下的适用性。基于此,提出一种基于光伏动态电流参考值的LVRT控制策略。首先,在建立两级式光伏并网系统及光伏电池P–U特性数学模型的基础上,分别对目前常用的基于定直流母线电压和基于光伏P–U特性曲线的LVRT控制的原理及不足进行了分析。其次,针对前级boost电路的控制构造了具有自适应收敛特性的光伏输出电流动态参考值以对光伏工作点进行直接调整。该策略无需对光伏P–U特性曲线数学模型进行求解,避免求解误差的同时加快了光伏动态响应速度。此外,在最大功率跟踪(MPPT)算法中引入故障解耦模块,在电网低电压故障期间对MPPT输出电压参考值进行锁定,避免MPPT无效运算带来的电压参考值偏移,使系统在故障结束时能以最快速度恢复至最大功率点。最后,通过仿真将所提策略与目前常用的基于定直流母线电压和基于光伏P–U特性曲线的LVRT控制策略在多种环境条件下进行对比。仿真结果表明:与定直流母线电压控制策略相比,所提策略下光伏动态响应快;与现有基于光伏P–U特性曲线的控制策略相比,所提策略不受P–U特性误差的影响,在辐照度变化尤其局部阴影条件下均能很好地实现低电压穿越。

一种宽输入范围高PSR带隙基准电路设计

从DC-DC芯片电路的实际设计需求出发,设计了一款输入电压范围在2.5~15 V的带隙基准电路。通过预调节电路的设计,带隙基准核输出的基准电压转化为一个稳定的电流源,形成的负反馈结构给带隙基准核自身提供供电电压,提高了电源电压范围上限;通过电压选择电路,在电源电压低于5 V时使带隙基准核直接由电源电压供电,拓宽了电源电压范围的下限。同时,预调节电路和带隙基准核中共源共栅结构为电路带来了良好的电源抑制特性。设计基于0.25μm BCD工艺,完成了原理图、版图设计以及仿真,结果表明设计在-55℃~125℃的温度范围内,可以输出稳定的0.8 V电压,温度系数为7.78 ppm/℃;低频条件下PSR达到159 dB,线性调整率为0.0012%。

软击穿对压控磁各向异性磁隧道结及其读电路性能影响

为了解决软击穿导致的压控磁各向异性磁隧道结(voltage-controlled magnetic anisotropy magnetic tunnel junction,VCMA-MTJ)及其读电路性能下降的问题,在对VCMA-MTJ软击穿机理深入分析的基础上,修正了VCMA-MTJ的电学模型,设计了一种具有固定参考电阻的VCMA-MTJ读电路和一种具有参考电阻调控单元的VCMA-MTJ读电路,研究了软击穿对VCMA-MTJ电阻R_(t)、隧穿磁阻比率M、软击穿时间T_(s)以及VCMA-MTJ读电路读错误率的影响。结果表明:软击穿的出现会导致R_(t)和M均随应力时间t的增加而降低,T_(s)随氧化层厚度t_(ox)的增大而缓慢增加,却随脉冲电压V_(b)的增大而迅速减少,与反平行态相比,平行态的T_(s)更短且M降低50%所需时间更少;具有固定参考电阻的VCMA-MTJ读电路可有效避免读“0”错误率的产生,但读“1”错误率却随t的增加而上升,而具有参考电阻调控单元的VCMA-MTJ读电路可在保持读“0”正确率的同时,对读“1”错误率改善达54%,在一定程度上削弱了软击穿对VCMA-MTJ读电路的影响。

基于低电压与高PSRR的带隙电压基准源设计

阐述对低电压、高电源抑制比(PSRR)的带隙电压基准源设计,分析带隙电压基准源的特点,结合原电路设计的局限性,设计了低电压、高PSRR的带隙电压基准源电路结构。仿真分析表明,仿真的结果和理论分析结果保持一致,所设计电路在低压模拟电路以及数字信号处理系统中有较好适用性。

高压交流断路器标准的主要差异分析

本文主要对GB/T 1984—2014与IEC 62271-100:2021的差异进行分析,主要针对文本差异和基本技术参量差异两个方面,其中文本差异主要分析了适用范围和规范性引用文件、使用条件以及术语和定义;基本技术参量差异主要分析了额定绝缘水平、温升限值、TRV参数以及试验参量的容差。通过以上几个方面的分析,加深对标准理解和规范检测认证。

基于改进NSGA-Ⅲ算法的抽油机井群控变频启动技术

为提升抽油机井群控变频启动运行的安全性,增加抽油机井的抽油量,研究基于改进NSGA-Ⅲ算法的抽油机井群控变频启动技术,降低变频启动的电压偏差,通过分析抽油机井群控变频启动条件,明确降低抽油机井群控变频电机与供电管网的电压偏差可以降低变频启动时的冲击电流,提升变频启动运行的安全性。以最小电压偏差与最大抽油量为目标函数,建立抽油机井群控变频电机启动转速确定模型;在NSGA-Ⅲ算法引入参考点选择策略,得到改进的NSGA-Ⅲ算法;用改进NSGA-Ⅲ算法求解转速确定模型,得到最小电压偏差与最大抽油量对应的变频电机启动转速;根据合闸时刻变频电机的相角差,得到变频电机合闸指令,并按照确定的转速启动抽油机井群控变频电机。实验证明:该技术可有效求解抽油机井群控变频电机转速确定模型,且反转世代距离较小、超体积较大,即该技术的收敛性与分布性较优;该技术可有效启动抽油机井群控变频电机,平均抽油量15.8 t/d,最大电压偏差260 V(DC)。

A 150-nA 13.4-ppm/℃switched-capacitor CMOS sub-bandgap voltage reference

A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 035-μm 3.3-V/5-V dual gate mixed-signal CMOS process.The proposed circuit generates a precise sub-bandgap voltage of 1 V.The temperature coefficient of the output voltage is 13.4 ppm/℃with the temperature varying from -20 to 80℃.The proposed circuit operates properly with the supply voltage down to 1.3 V,and consumes 150 nA at room temperature.The line regulation is 0.27%/V.The power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB,respectively.The chip area is 0.2 mm^2.

A reference voltage in capacitor–resister hybrid SAR ADC for front-end readout system of CZT detector

An on-chip reference voltage has been designed in capacitor–resister hybrid SAR ADC for CZT detector with the TSMC 0.35μm 2P4M CMOS process.The voltage reference has a dynamic load since using variable capacitors and resistances,which need a large driving ability to deal with the current related to the time and sampling rate.Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR.However,it is not enough and overall,it needs to consider the output driving ability.The proposed voltage reference is realized by the band-gap reference,voltage generator and output buffer.Apart from a low temperature coefficient and high PSRR,it has the features of a large driving ability and low power consumption.What is more,for CZT detectors application in space,a radiation-hardened design has been considered.The measurement results show that the output reference voltage of the buffer is 4.096 V.When the temperature varied from 0 to 80℃,the temperature coefficient is 12.2 ppm/℃.The PSRR was 70 d B@100 k Hz.The drive current of the reference can reach up to 10 m A.The area of the voltage reference in the SAR ADC chip is only 449614 m^2.The total power consumption is only 1.092 m W.

A new curvature compensation technique for CMOS voltage reference using |V_(GS)| and △V_(BE)

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source–gate voltage︱VGS︱_p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate–source voltages︱VGS︱_n of NMOS transistors in the subthreshold region and the difference between two base–emitter voltages △V_(BE) of bipolar junction transistors(BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area.The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/℃ without trimming,over a temperature range from -40 to 120 ℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio(PSRR) is 31:2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm^2.

A Super Performance Bandgap Voltage Reference with Adjustable Output for DC-DC Converter

This paper presents a super performance bandgap voltage reference for DC-DC converter with adjustable output. It generates a wide range of voltage reference ranging from sub-1V to 1.2217V and has a low temperature coefficient of 2.3×10 -5/K over the temperature variation using the current feedback and resistive subdivision. In addition, the power supply rejection ration of the proposed bandgap voltage reference is 78dB. When supply voltage varies from 2.5V to 6V, output VREF is 1.221685±0.055mV.