High on-state current p-type tunnel effect transistor based on doping modulation

To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.

Characteristic enhancement in tunnel field-effect transistors via introduction of vertical graded source

A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two decades higher than that of the conventional GaAs TFETs without sacrificing the subthreshold swing(SS)due to the improved band-to-band tunneling efficiency.Compared with the conventional TFETs,much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 mV/dec.Furthermore,the minimum SS about 20 mV/dec indicates its promising potential for further ultralow power applications.

Impact of low/high-κ spacer-source overlap on characteristics of tunnel dielectric based tunnel field-effect transistor

The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.

Comparison of band-to-band tunneling models in Si and Si–Ge junctions

We compared several different band-to-band tunneling （BTBT） models with both Sentaurus and the two-dimensional full-band Monte Carlo simulator in Si homo-junctions and Si-Ge hetero-junctions. It was shown that in Si homo-junctions, different models could achieve similar results. However, in the Si-Ge hetero-junctions, there were significant differences among these models at high reverse biases （over 2 V）. Compared to the nonlocal model, the local models in Sentaurus underrated the BTBT rate distinctly, and the Monte Carlo method was shown to give a better approximation. Additionally, it was found that in the Si region near the interface of the Si-Ge hetero-junctions, the direct tunneling rates increased largely due to the interaction of the band structures of Si and Ge.

一种新型隧穿场效应晶体管

提出了一种新型隧穿场效应晶体管(TFET)结构,该结构通过在常规TFET靠近器件栅氧化层一侧的漏-体结界面引入一薄层二氧化硅(隔离区),从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿(BTBT),减弱TFET的双极效应,实现大幅度降低器件泄漏电流的目的。利用TCAD仿真工具对基于部分耗尽绝缘体上硅(PDSOI)和全耗尽绝缘体上硅(FDSOI)的TFET和新型TFET结构进行了仿真与对比。仿真结果表明,当隔离区宽度为2 nm,高度大于10 nm时,可阻断PDSOI TFET的BTBT,其泄漏电流下降了4个数量级;而基于FDSOI的TFET无法彻底消除BTBT和双极效应,其泄漏电流下降了2个数量级。因此新型结构更适合于PDSOI TFET。

Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF（IDIFF,MAX） varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.

Hetero-gate-dielectric double gate junctionless transistor(HGJLT)with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Total ionizing dose induced single transistor latchup in 130-nm PDSOI input/output NMOSFETs

Total ionizing dose induced single transistor latchup effects for 130 nm partially depleted silicon-on-insulator （PDSOI） NMOSFETs with the bodies floating were studied in this work. The latchup phenomenon strongly correlates with the bias configuration during irradiation. It is found that the high body doping concentration can make the devices less sensitive to the single transistor latchup effect, and the onset drain voltage at which latchup occurs can degrade as the total dose level rises. The mechanism of band-to-band tunneling （BBT） has been discussed. Two-dimensional simulations were conducted to evaluate the BBT effect. It is demonstrated that BBT combined with the positive trapped charge in the buried oxide （BOX） contributes a lot to the latchup effect.

一种带有斜向扩展源的双栅隧穿场效应晶体管

设计并研究了一种带有轻掺杂漏(LDD)和斜向扩展源(OES)的双栅隧穿场效应晶体管(DG-TFET),并利用Sentaurus TCAD仿真工具对栅长及扩展源长度等关键参数进行了仿真分析。对比了该器件与传统TFET的亚阈值摆幅、关态电流和开关电流比,并从器件的带带隧穿概率分析其优势。仿真结果表明,该器件的最佳数值开关电流比及亚阈值摆幅分别可达3.56×10^(12)和24.5 mV/dec。另外,该DG-TFET在双极性电流和接触电阻方面性能良好,且具有较快的转换速率和较低的功耗。

具有夹层的垂直U型栅极TFET的设计

通过使用工艺计算机辅助设计(TCAD)仿真技术提出了一种新型的带有夹层的垂直U型栅极隧穿场效应晶体管(TFET)结构。该器件是通过优化基于Ge的栅极金属核垂直纳米线TFET结构获得的。通过在沟道中增加重掺杂夹层,器件的平均亚阈值摆幅(SS_(avg))得到了改善;又通过改变器件的源极和漏极材料,器件的开关电流比(I_(on)/I_(off))得到了改善。对夹层的掺杂浓度和厚度以及沟道的高度也进行了优化。最终优化后的器件开态电流为220μA/μm,关态电流为3.08×10^(-10)μA/μm,SS_(avg)为8.6 mV/dec,表现出了优越的性能。与初始器件相比,该器件的SS_(avg)减小了77%,I_(on)/I_(off)增加了两个数量级以上。此外,提出了针对该器件的可行的制备工艺步骤。因此,认为该器件是在超低功耗应用中非常具有潜力的候选器件。

Temperature dependent I_(DS)–V_(GS) characteristics of an N-channel Si tunneling field-effect transistor with a germanium source on Si(110) substrate

We fabricated n-type Si-based TFETs with a Ge source on Si（110） substrate. The temperature dependent IDS-VGS characteristics of a TFET formed on Si（110） are investigated in the temperature range of 210 to 300 K. A study of the temperature dependence of/Leakage indicates that/Leakage is mainly dominated by the Shockley-Read- Hall （SRH） generation-recombination current of the n＋ drain-Si substrate junction, ION increases monotonically with temperature, which is attributed to a reduction of the bandgap at the tunneling junction and an enhancement of band-to-band tunneling rate. The subthreshold swing S for trap assisted tunneling （TAT） current and band-to- band tunneling （BTBT） current shows the different temperature dependence. The subthreshold swing S for the TAT current degrades with temperature, while the S for BTBT current is temperature independent.

GeSn/Ge异质无结型隧穿场效应晶体管

提出了一种新型GeSn/Ge异质无结型隧穿场效应晶体管(GeSn/Ge-hetero JLTFET)。该器件结合了直接窄带隙材料GeSn与传统JLTFET的优点,利用功函数工程诱导器件本征层感应出空穴(p型)或电子(n型),在无需掺杂的前提下,形成器件的源区、沟道区和漏区,从而避免了使用复杂的离子注入工艺和引入随机掺杂波动。该器件减小了隧穿路径宽度,提高了开态电流,获得了更陡峭的亚阈值摆幅。仿真结果表明GeSn/Ge-hetero JLTFET的开态电流为7.08×10^-6 A/μm,关态电流为3.62×10^-14 A/μm,亚阈值摆幅为37.77 mV/dec。同时,GeSn/Ge-hetero JLTFET的相关参数(跨导、跨导生成因子、截止频率和增益带宽积)的性能也优于传统器件。

一种新型异质结双栅隧穿场效应晶体管

文章提出一种新型Si/Ge异质结双栅隧穿场效应晶体管(GP_Si/Ge_DGTFET)。该器件在异质结的基础上加入凹槽型pocket结构,禁带宽度较窄的Ge材料可以使器件拥有更低的亚阈值摆幅和更大的开态电流,同时pocket结构的引入可以进一步降低隧穿势垒。基于Sentaurus TCAD仿真软件,将该新型器件与传统Si/Ge异质结双栅隧穿场效应晶体管(Si/Ge_DGTFET)进行对比。仿真结果表明,该新器件拥有更好的亚阈值摆幅和开关特性,其开态电流为6.0×10^(-5) A/μm,关态电流约为10^(-14) A/μm,平均亚阈值摆幅达到35.36 mV/dec。

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.

Temperature effect on hetero structure junctionless tunnel FET

For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.

High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply

We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.

Performance analysis of charge plasma based dual electrode tunnel FET

This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDLTEFT gives the superior results with high ON state current （/ON - 0.56 mA/um）, ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing （AV-SS -- 48 mV/dec）. The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

A double-gate tunnel field-effect transistor （DG tunnel FET） has been designed and investigated for various channel materials such as silicon （Si）, gallium arsenide （GaAs）, alminium gallium arsenide （A1xGa1-xAs） and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are com- pared on the basis of inverse subthreshold slope （SS）, ION/IoFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the A1xGa1-xAs based DG tunnel FET provides a better ION/IOFF current ratio （2.51 × 10^6） as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.