To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the infl...To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.展开更多
The tunneling field-effect transistor(TFET) is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional(2D) models are used...The tunneling field-effect transistor(TFET) is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional(2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.展开更多
A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two d...A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two decades higher than that of the conventional GaAs TFETs without sacrificing the subthreshold swing(SS)due to the improved band-to-band tunneling efficiency.Compared with the conventional TFETs,much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 mV/dec.Furthermore,the minimum SS about 20 mV/dec indicates its promising potential for further ultralow power applications.展开更多
The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents...The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.展开更多
We compared several different band-to-band tunneling (BTBT) models with both Sentaurus and the two-dimensional full-band Monte Carlo simulator in Si homo-junctions and Si-Ge hetero-junctions. It was shown that in Si...We compared several different band-to-band tunneling (BTBT) models with both Sentaurus and the two-dimensional full-band Monte Carlo simulator in Si homo-junctions and Si-Ge hetero-junctions. It was shown that in Si homo-junctions, different models could achieve similar results. However, in the Si-Ge hetero-junctions, there were significant differences among these models at high reverse biases (over 2 V). Compared to the nonlocal model, the local models in Sentaurus underrated the BTBT rate distinctly, and the Monte Carlo method was shown to give a better approximation. Additionally, it was found that in the Si region near the interface of the Si-Ge hetero-junctions, the direct tunneling rates increased largely due to the interaction of the band structures of Si and Ge.展开更多
A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has...A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF(IDIFF,MAX) varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.展开更多
We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects &band-to-band tunnelli...We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects &band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n-p-n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.展开更多
Total ionizing dose induced single transistor latchup effects for 130 nm partially depleted silicon-on-insulator (PDSOI) NMOSFETs with the bodies floating were studied in this work. The latchup phenomenon strongly c...Total ionizing dose induced single transistor latchup effects for 130 nm partially depleted silicon-on-insulator (PDSOI) NMOSFETs with the bodies floating were studied in this work. The latchup phenomenon strongly correlates with the bias configuration during irradiation. It is found that the high body doping concentration can make the devices less sensitive to the single transistor latchup effect, and the onset drain voltage at which latchup occurs can degrade as the total dose level rises. The mechanism of band-to-band tunneling (BBT) has been discussed. Two-dimensional simulations were conducted to evaluate the BBT effect. It is demonstrated that BBT combined with the positive trapped charge in the buried oxide (BOX) contributes a lot to the latchup effect.展开更多
We fabricated n-type Si-based TFETs with a Ge source on Si(110) substrate. The temperature dependent IDS-VGS characteristics of a TFET formed on Si(110) are investigated in the temperature range of 210 to 300 K. A...We fabricated n-type Si-based TFETs with a Ge source on Si(110) substrate. The temperature dependent IDS-VGS characteristics of a TFET formed on Si(110) are investigated in the temperature range of 210 to 300 K. A study of the temperature dependence of/Leakage indicates that/Leakage is mainly dominated by the Shockley-Read- Hall (SRH) generation-recombination current of the n+ drain-Si substrate junction, ION increases monotonically with temperature, which is attributed to a reduction of the bandgap at the tunneling junction and an enhancement of band-to-band tunneling rate. The subthreshold swing S for trap assisted tunneling (TAT) current and band-to- band tunneling (BTBT) current shows the different temperature dependence. The subthreshold swing S for the TAT current degrades with temperature, while the S for BTBT current is temperature independent.展开更多
We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain ...We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gatel ) with two different work functions (gate = 4.2 eV, gatel = 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.展开更多
We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage)...We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.展开更多
For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute devic...For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope (〈 60 mV/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.展开更多
We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the p...We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.展开更多
This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDL...This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (/ON - 0.56 mA/um), ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing (AV-SS -- 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.展开更多
A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (A1xGa1-xAs...A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (A1xGa1-xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are com- pared on the basis of inverse subthreshold slope (SS), ION/IoFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the A1xGa1-xAs based DG tunnel FET provides a better ION/IOFF current ratio (2.51 × 10^6) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.展开更多
基金Project supported by the Key Research and Development Program of Shaanxi(Grant No.2021GY-010)the National Defense Science and Technology Foundation Strengthening Program of China(Grant No.2019-XXXX-XX-236-00).
文摘To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.
基金Project supported by the National Ministries and Commissions,China (Grant Nos. 51308040203 and 6139801)the Fundamental Research Funds for the Central Universities,China (Grant Nos. 72105499 and 72104089)the Natural Science Basic Research Plan in Shaanxi Province,China (Grant No. 2010JQ8008)
文摘The tunneling field-effect transistor(TFET) is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional(2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.
基金Project supported by the National Natural Science Foundation of China(Grant No.90304190002).
文摘A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two decades higher than that of the conventional GaAs TFETs without sacrificing the subthreshold swing(SS)due to the improved band-to-band tunneling efficiency.Compared with the conventional TFETs,much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 mV/dec.Furthermore,the minimum SS about 20 mV/dec indicates its promising potential for further ultralow power applications.
基金Projects(61574109,61204092)supported by the National Natural Science Foundation of China
文摘The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.
文摘We compared several different band-to-band tunneling (BTBT) models with both Sentaurus and the two-dimensional full-band Monte Carlo simulator in Si homo-junctions and Si-Ge hetero-junctions. It was shown that in Si homo-junctions, different models could achieve similar results. However, in the Si-Ge hetero-junctions, there were significant differences among these models at high reverse biases (over 2 V). Compared to the nonlocal model, the local models in Sentaurus underrated the BTBT rate distinctly, and the Monte Carlo method was shown to give a better approximation. Additionally, it was found that in the Si region near the interface of the Si-Ge hetero-junctions, the direct tunneling rates increased largely due to the interaction of the band structures of Si and Ge.
基金Project supported by the National High Technology Research and Development Program of China (Grant No 2003AA1Z1630) and the National Natural Science Foundation of China (Grant No 60376024).
文摘A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF(IDIFF,MAX) varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.
文摘We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects &band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n-p-n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.
基金Project supported by Shanghai Municipal Natural Science Foundation,China(Grant No.15ZR1447100)
文摘Total ionizing dose induced single transistor latchup effects for 130 nm partially depleted silicon-on-insulator (PDSOI) NMOSFETs with the bodies floating were studied in this work. The latchup phenomenon strongly correlates with the bias configuration during irradiation. It is found that the high body doping concentration can make the devices less sensitive to the single transistor latchup effect, and the onset drain voltage at which latchup occurs can degrade as the total dose level rises. The mechanism of band-to-band tunneling (BBT) has been discussed. Two-dimensional simulations were conducted to evaluate the BBT effect. It is demonstrated that BBT combined with the positive trapped charge in the buried oxide (BOX) contributes a lot to the latchup effect.
基金Project supported by the Fundamental Research Funds for the Central Universities(Nos.106112013CDJZR120015,106112013CDJZR120017)
文摘We fabricated n-type Si-based TFETs with a Ge source on Si(110) substrate. The temperature dependent IDS-VGS characteristics of a TFET formed on Si(110) are investigated in the temperature range of 210 to 300 K. A study of the temperature dependence of/Leakage indicates that/Leakage is mainly dominated by the Shockley-Read- Hall (SRH) generation-recombination current of the n+ drain-Si substrate junction, ION increases monotonically with temperature, which is attributed to a reduction of the bandgap at the tunneling junction and an enhancement of band-to-band tunneling rate. The subthreshold swing S for trap assisted tunneling (TAT) current and band-to- band tunneling (BTBT) current shows the different temperature dependence. The subthreshold swing S for the TAT current degrades with temperature, while the S for BTBT current is temperature independent.
文摘We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gatel ) with two different work functions (gate = 4.2 eV, gatel = 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.
文摘We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.
文摘For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope (〈 60 mV/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.
文摘We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.
文摘This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (/ON - 0.56 mA/um), ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing (AV-SS -- 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.
文摘A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (A1xGa1-xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are com- pared on the basis of inverse subthreshold slope (SS), ION/IoFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the A1xGa1-xAs based DG tunnel FET provides a better ION/IOFF current ratio (2.51 × 10^6) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.