The effect of the deposition temperature of the buffer layer In_2S_3 on the band alignment of CZTS/In_2S_3 heterostructures and the solar cell performance have been investigated.The In_2S_3 films are prepared by therm...The effect of the deposition temperature of the buffer layer In_2S_3 on the band alignment of CZTS/In_2S_3 heterostructures and the solar cell performance have been investigated.The In_2S_3 films are prepared by thermal evaporation method at temperatures of 30,100,150,and 200 ℃,respectively.By using x-ray photoelectron spectroscopy（XPS）,the valence band offsets（VBO） are determined to be-0.28 ±0.1,-0.28 ±0.1,-0.34 ±0.1,and-0.42 ±0.1 eV for the CZTS/In_2S_3heterostructures deposited at 30,100,150,and 200 ℃,respectively,and the corresponding conduction band offsets（CBO）are found to be 0.3 ±0.1,0.41 ±0.1,0.22±0.1,and 0.01 ±0.1 eV,respectively.The XPS study also reveals that interdiffusion of In and Cu occurs at the interface of the heterostructures,which is especially serious at 200 ℃ leading to large amount of interface defects or the formation of CuInS_2 phase at the interface.The CZTS solar cell with the buffer layer In_2S_3 deposited at 150 ℃ shows the best performance due to the proper CBO value at the heterostructure interface and the improved crystal quality of In_2S_3 film induced by the appropriate deposition temperature.The device prepared at 100 ℃presents the poorest performance owing to too high a value of CBO.It is demonstrated that the deposition temperature is a crucial parameter to control the quality of the solar cells.展开更多
The partial charge simulation method is presented to solve the characteristicimpedance of the transmission line of specific cross section with an offset inner conductor.Thismethod has a higher accuracy due to the accu...The partial charge simulation method is presented to solve the characteristicimpedance of the transmission line of specific cross section with an offset inner conductor.Thismethod has a higher accuracy due to the accurate satisfaction of the boundary condition on theouter conductor.The combined method of the Gauss elimination and optimization is used tosolve the equation of charge simulation,and it is an effective method for increasing the accuracyand assuring the convergence.The Green’s functions of five transmission lines(i.e,with circular,elliptic,rectangular,trough and slab conductor)are given.展开更多
An investigation on the ventral diverterless high offset S-shaped inlet is carried out at Mach numbers from 0.600 to 1.534, angles of attack from -4° to 9.4°, and yaw angles from 0° to 8°. Results ...An investigation on the ventral diverterless high offset S-shaped inlet is carried out at Mach numbers from 0.600 to 1.534, angles of attack from -4° to 9.4°, and yaw angles from 0° to 8°. Results indicate： （1） a large region of low total pressure exists at the lower part of the inlet exit caused by the counter-rotating vortices in the S-shaped duct; （2） the performances of the inlet at Mach number 1.000 reach almost the highest, so the propulsion system could work efficiently in terms of aerodynamics; （3） the total pressure recovery increases slowly at first and then remains unvaried as the Mach number rises from 0.6 to 1.0, however, it does in an opposite manner in the conventional diverter-equipped S-shaped inlet; （4） the performances of the inlet are generally insensitive to angles of attack from -4° to 9.4° and yaw angles from 0° to 8° at Mach number 0.850, and angles of attack from -2° to 6° and yaw angles from 0° to 5° at Mach number 1.534.展开更多
In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed....In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed. Critical parameters,such as capacitor mismatch,clock jitter are proposed and simulated. The pipelined ADC system is divided into five parts,clock generator,sample and hold( S/H) circuit,multiplying digital-to-analog converters( MDAC),backend,and digital correction. These blocks introduce several interferences,which attenuate performance of pipelined ADC severely. Modeling and simulations of these disturbance sources are presented particularly. A new model of S/H is introduced. Results derived from simulations can supervise design and optimization of the ADC system.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61574038 and 61674038)the Natural Science Foundation of Fujian Province,China(Grant No.2014J05073)
文摘The effect of the deposition temperature of the buffer layer In_2S_3 on the band alignment of CZTS/In_2S_3 heterostructures and the solar cell performance have been investigated.The In_2S_3 films are prepared by thermal evaporation method at temperatures of 30,100,150,and 200 ℃,respectively.By using x-ray photoelectron spectroscopy（XPS）,the valence band offsets（VBO） are determined to be-0.28 ±0.1,-0.28 ±0.1,-0.34 ±0.1,and-0.42 ±0.1 eV for the CZTS/In_2S_3heterostructures deposited at 30,100,150,and 200 ℃,respectively,and the corresponding conduction band offsets（CBO）are found to be 0.3 ±0.1,0.41 ±0.1,0.22±0.1,and 0.01 ±0.1 eV,respectively.The XPS study also reveals that interdiffusion of In and Cu occurs at the interface of the heterostructures,which is especially serious at 200 ℃ leading to large amount of interface defects or the formation of CuInS_2 phase at the interface.The CZTS solar cell with the buffer layer In_2S_3 deposited at 150 ℃ shows the best performance due to the proper CBO value at the heterostructure interface and the improved crystal quality of In_2S_3 film induced by the appropriate deposition temperature.The device prepared at 100 ℃presents the poorest performance owing to too high a value of CBO.It is demonstrated that the deposition temperature is a crucial parameter to control the quality of the solar cells.
文摘The partial charge simulation method is presented to solve the characteristicimpedance of the transmission line of specific cross section with an offset inner conductor.Thismethod has a higher accuracy due to the accurate satisfaction of the boundary condition on theouter conductor.The combined method of the Gauss elimination and optimization is used tosolve the equation of charge simulation,and it is an effective method for increasing the accuracyand assuring the convergence.The Green’s functions of five transmission lines(i.e,with circular,elliptic,rectangular,trough and slab conductor)are given.
基金National Basic Research Program of China (5130802)
文摘An investigation on the ventral diverterless high offset S-shaped inlet is carried out at Mach numbers from 0.600 to 1.534, angles of attack from -4° to 9.4°, and yaw angles from 0° to 8°. Results indicate： （1） a large region of low total pressure exists at the lower part of the inlet exit caused by the counter-rotating vortices in the S-shaped duct; （2） the performances of the inlet at Mach number 1.000 reach almost the highest, so the propulsion system could work efficiently in terms of aerodynamics; （3） the total pressure recovery increases slowly at first and then remains unvaried as the Mach number rises from 0.6 to 1.0, however, it does in an opposite manner in the conventional diverter-equipped S-shaped inlet; （4） the performances of the inlet are generally insensitive to angles of attack from -4° to 9.4° and yaw angles from 0° to 8° at Mach number 0.850, and angles of attack from -2° to 6° and yaw angles from 0° to 5° at Mach number 1.534.
基金Supported by the National Basic Research Program of China(No.2010CB327404)
文摘In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed. Critical parameters,such as capacitor mismatch,clock jitter are proposed and simulated. The pipelined ADC system is divided into five parts,clock generator,sample and hold( S/H) circuit,multiplying digital-to-analog converters( MDAC),backend,and digital correction. These blocks introduce several interferences,which attenuate performance of pipelined ADC severely. Modeling and simulations of these disturbance sources are presented particularly. A new model of S/H is introduced. Results derived from simulations can supervise design and optimization of the ADC system.
