Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial tr...Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.展开更多
Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique wa...Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique was adopted to investigate integration with other complicated circuits.Using a unique XOR gate,the recommended circuit’s cell complexity has been decreased.The findings produced using the QCADesigner-2.0.3,a reliable simulation tool,prove the effectiveness of the current structure over earlier designs by considering the number of cells deployed,the area occupied,and the latency as design metrics.In addition,the popular tool QCAPro was used to estimate the energy dissipation of the proposed design.The proposed technique reduces the occupied space by∼40%,improves cell complexity by∼20%,and reduces energy dissipation by∼1.8 times(atγ=1.5EK)compared to the current scalable designs.This paper also studied the suggested structure’s energy dissipation and compared it to existing works for a better performance evaluation.展开更多
BACKGROUND Juvenile systemic lupus erythematosus(SLE)is a severe,life-threatening disease.However,the role of rituximab in managing juvenile SLE remains undefined,although early biological intervention may improve dis...BACKGROUND Juvenile systemic lupus erythematosus(SLE)is a severe,life-threatening disease.However,the role of rituximab in managing juvenile SLE remains undefined,although early biological intervention may improve disease outcomes.AIM To assess the differences in the outcomes of different types of rituximab administration(early and late).METHODS In this retrospective cohort study,the information of 36 children with SLE with administration(LRA)was analyzed.We compared initial disease characteristics at onset,at baseline(start of rituximab),and at the end of the study(EOS)at 12 months,as well as outcomes and treatment characteristics.RESULTS The main differences at baseline were a higher daily median dose of corticosteroids,increased MAS frequency,and a higher Systemic Lupus Erythematosus Disease Activity Index(SLEDAI)in the ERA group.No differences in the main SLE outcomes between groups at the EOS were observed.The part of lupus nephritis patients who achieved remission changed from 44%to 31%in ERA and 32%to 11%in the LRA group.Patients with ERA had a shorter time to achieve low daily corticosteroid dose(≤0.2 mg/kg)at 1.2(0.9;1.4)years compared to 2.8(2.3;4.0)years(P=0.000001)and higher probability to achieve this low dose[hazard ratio(HR)=57.8(95%confidence interval(CI):7.2-463.2),P=0.00001 and remission(SLEDAI=0);HR=37.6(95%CI:4.45-333.3),P=0.00001].No differences in adverse events,including severe adverse events,were observed.CONCLUSION ERA demonstrated a better steroid-sparing effect and a possibility of earlier remission or low disease activity,except for lupus nephritis.Further investigations are required.展开更多
研究了光电探测器(PD)的结构、性能以及后续放大电路,实现了塑料光纤通信的高速单片集成光接收芯片。首先,根据工艺流程和参数,采用器件模拟软件对PD结构进行了建模,并对其光谱响应度和结电容进行了理论推导及仿真。基于Cadence/spectr...研究了光电探测器(PD)的结构、性能以及后续放大电路,实现了塑料光纤通信的高速单片集成光接收芯片。首先,根据工艺流程和参数,采用器件模拟软件对PD结构进行了建模,并对其光谱响应度和结电容进行了理论推导及仿真。基于Cadence/spectre软件和仿真得到的PD参数对由跨阻放大器、限幅放大器和输出缓冲电路组成的后续放大电路进行了协同设计。采用0.5μm BCD(Bipolar,CMOS and DMOS)工艺对单个PD以及PD和后续放大电路单片集成电路进行了流片、封装和测试。结果表明:PD的光谱响应曲线的峰值波长和仿真结果较一致,约为700nm,PD结构更适合短波长探测;PD的结电容随着反向电压的增大而减小,结电容越大,光接收芯片的带宽越小;对于650nm的入射光,在小于10-9的误码率条件下,光接收机的灵敏度为-14dBm;最后得到了150Mb/s速率的清晰眼图。实验结果显示,设计的高速单片集成光接收机可以应用于百兆速率光纤入户通信系统。展开更多
A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9...A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.展开更多
文摘Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.
文摘针对超密集网络(ultra dense network,UDN)中基站密集部署导致的严重层间干扰问题,构建了考虑频谱复用和共信道干扰条件下最大化系统总吞吐量问题模型,提出了一种基于块坐标下降(block coordinate descent,BCD)法的联合频谱资源优化(joint resource optimization based on BCD,JROBB)方法。该方法将原问题分解为分簇、子信道分配和功率分配三个子问题,通过BCD法迭代优化子信道分配和功率分配,逼近原问题的最优解。仿真分析表明,在复杂度提升有限的情况下,系统总吞吐量比现有典型算法平均至少提升22%,可以有效提升频谱利用率。
文摘Code converters are essential in digital nano communication;therefore,a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper.A QCA clockphase-based design technique was adopted to investigate integration with other complicated circuits.Using a unique XOR gate,the recommended circuit’s cell complexity has been decreased.The findings produced using the QCADesigner-2.0.3,a reliable simulation tool,prove the effectiveness of the current structure over earlier designs by considering the number of cells deployed,the area occupied,and the latency as design metrics.In addition,the popular tool QCAPro was used to estimate the energy dissipation of the proposed design.The proposed technique reduces the occupied space by∼40%,improves cell complexity by∼20%,and reduces energy dissipation by∼1.8 times(atγ=1.5EK)compared to the current scalable designs.This paper also studied the suggested structure’s energy dissipation and compared it to existing works for a better performance evaluation.
基金Supported by Ministry of Science and Higher Education of the Russian Federation,No.075-15-2022-301the Russian Science Foundation Grant,No.22-45-08004.
文摘BACKGROUND Juvenile systemic lupus erythematosus(SLE)is a severe,life-threatening disease.However,the role of rituximab in managing juvenile SLE remains undefined,although early biological intervention may improve disease outcomes.AIM To assess the differences in the outcomes of different types of rituximab administration(early and late).METHODS In this retrospective cohort study,the information of 36 children with SLE with administration(LRA)was analyzed.We compared initial disease characteristics at onset,at baseline(start of rituximab),and at the end of the study(EOS)at 12 months,as well as outcomes and treatment characteristics.RESULTS The main differences at baseline were a higher daily median dose of corticosteroids,increased MAS frequency,and a higher Systemic Lupus Erythematosus Disease Activity Index(SLEDAI)in the ERA group.No differences in the main SLE outcomes between groups at the EOS were observed.The part of lupus nephritis patients who achieved remission changed from 44%to 31%in ERA and 32%to 11%in the LRA group.Patients with ERA had a shorter time to achieve low daily corticosteroid dose(≤0.2 mg/kg)at 1.2(0.9;1.4)years compared to 2.8(2.3;4.0)years(P=0.000001)and higher probability to achieve this low dose[hazard ratio(HR)=57.8(95%confidence interval(CI):7.2-463.2),P=0.00001 and remission(SLEDAI=0);HR=37.6(95%CI:4.45-333.3),P=0.00001].No differences in adverse events,including severe adverse events,were observed.CONCLUSION ERA demonstrated a better steroid-sparing effect and a possibility of earlier remission or low disease activity,except for lupus nephritis.Further investigations are required.
文摘研究了光电探测器(PD)的结构、性能以及后续放大电路,实现了塑料光纤通信的高速单片集成光接收芯片。首先,根据工艺流程和参数,采用器件模拟软件对PD结构进行了建模,并对其光谱响应度和结电容进行了理论推导及仿真。基于Cadence/spectre软件和仿真得到的PD参数对由跨阻放大器、限幅放大器和输出缓冲电路组成的后续放大电路进行了协同设计。采用0.5μm BCD(Bipolar,CMOS and DMOS)工艺对单个PD以及PD和后续放大电路单片集成电路进行了流片、封装和测试。结果表明:PD的光谱响应曲线的峰值波长和仿真结果较一致,约为700nm,PD结构更适合短波长探测;PD的结电容随着反向电压的增大而减小,结电容越大,光接收芯片的带宽越小;对于650nm的入射光,在小于10-9的误码率条件下,光接收机的灵敏度为-14dBm;最后得到了150Mb/s速率的清晰眼图。实验结果显示,设计的高速单片集成光接收机可以应用于百兆速率光纤入户通信系统。
文摘A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.
