Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Progressive current degradation and breakdown behavior in GaN LEDs under high reverse bias stress

The progressive current degradation and breakdown behaviors of GaN-based light emitting diodes under high reversebias stress are studied by combining the electrical, optical, and surface morphology characterizations. The current features a typical “soft breakdown” behavior, which is linearly correlated to an increase of the accumulative number of electroluminescence spots. The time-to-failure for each failure site approximately obeys a Weibull distribution with slopes of about 0.67 and 4.09 at the infant and wear-out periods, respectively. After breakdown, visible craters can be observed at the device surface as a result of transient electrostatic discharge. By performing focused ion beam cuts coupled with scan electron microscope, we observed a local current shunt path in the surface layer, caused by the rapid microstructure deterioration due to significant current heating effect, consistent well with the optical beam induced resistance change observations.

EFFECT OF BIAS STRESS ON NON-LINEAR INTERNAL FRICTION OF Al-Mg ALLOY

The influence of longitudinal and torsional bias stresses on anomalous amplitude-dependent internal friction was studied.The longitudinal bias stress may always weaken the anomalous amplitude-dependent effect,while the torsional one may induce different effects from differ- ent directions applied.Bias stress effect exhibits only in properly heat treated and cold worked ahoy specimens.The anomalous amplitude-dependent internal friction peaks,P_3,P_2 and P_1, are found to be related closely to slant dislocation kink chains.Thus,the application of bias stress to internal friction would be contributed to the study on dislocation structure.

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress(NBS)reliability of n-type polycrystalline silicon(poly-Si)thin-film transistors(TFTs)with a distinct defective grain boundary(GB)in the channel is investigated.Results show that conventional NBS degradation with negative shift of the transfer curves is absent.The on-state current is decreased,but the subthreshold characteristics are not affected.The gate bias dependence of the drain leakage current at V_(ds)of 5.0 V is suppressed,whereas the drain leakage current at V_(ds)of 0.1 V exhibits obvious gate bias dependence.As confirmed via TCAD simulation,the corresponding mechanisms are proposed to be trap state generation in the GB region,positive-charge local formation in the gate oxide near the source and drain,and trap state introduction in the gate oxide.

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress(NBS)is observed for amorphous InGaZnO(a-IGZO)thin-film transistors(TFTs),which can recover in a short time.After comparing with the degradation phenomena under negative bias illumination stress(NBIS),positive bias stress(PBS),and positive bias illumination stress(PBIS),degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies(V_(o)^(+))in addition to the commonly reported doubly charged oxygen vacancies(V_(o)^(2+)).Furthermore,the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of V_(o)^(+)under positive gate bias.The proposed degradation mechanisms are verified by TCAD simulation.

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.

Bias Effects on the Reynolds Stress Using the Multi-Purpose Probe in IR-T1 Tokamak

The effect of the positive bias on Reynolds stress （RS） and its effect on the radial turbulent transport at the edge plasma （r/a =0.9） and scrape-off layer （SOL） region of plasma in tokamak are investigated. The radial and poloidal electric fields （Sr, Ep） and ion saturation current （Is） are measured by multi-purpose probe （MPP）. This probe is fabricated and constructed for the first time in the IR-T1 tokamak. The most advantage of this probe is that the variations of Er and Ep can be measured in different radii at the single shot. Thus the information of different radii can be compared with high precision. The bias voltage is fixed at Vbias = 200 V and it has been applied with the limiter bias that is fixed in r/a = 0.9. Moreover, the phase difference between radial and poloidal electric fields, and temporal evolution of the RS .spectrum detected by MPP are calculated. RS magnitude on the edge （r/a = 0.9） is more than its value in the SOL （r/a = 1.02）. With the applied bias 200 V, ItS and the magnitude of the phase difference between Er and Ep are increased, while the radial turbulent transport is decreased simultaneously. Thus it can be concluded that RS affects radial turbulence. Temporal evolution of the RS spectrum shows that the frequency of RS is increased and reaches its highest value at r/a=0.9 in the presence of bias.

Influence of Temperature and Pentacene Thickness on the Electrical Parameters in Top Gate Organic Thin Film Transistor

In this contribution, we report on the effect of pentacene thickness and temperature on the performance of top gate transistors. We first investigated the temperature dependence of the transport properties in the temperature range of 258 K - 353 K. The electrical characteristics showed that the threshold voltage (VT) and the onset voltage (Von) remain unchanged. However, the subthreshold current (Ioff), the on-current (Ion) and the field effect mobility (μ) are highly affected with a slight deterioration of subthreshold slope. We observed Arrhenius-like behavior suggesting a thermally activated mobility with an activation energy EA = 68 meV. Moreover the dependence of the charge carrier mobility on the organic semiconductor thickness has also been studied. The mobility decreased as the pentacene thickness increases whereas the threshold voltage and Ioff current remain minimally affected. In order to understand the transport properties and in view to put in light morphology peculiarities of pentacene, AFM images were performed. It turns out that the pentacene grain sizes are smaller and disorganized as the film thickness increases, and charge carriers are more prone to be trapped, leading to decrease the field effect mobility and the Ion current. The devices were also tested under bias stress and the transistors with low thicknesses exhibited a relatively good electrical stability compared to those with high pentacene thicknesses. This work points out the influence of temperature, semiconductor thickness and bias stress effect on the device performance and stability of transistor using top gate configuration.

Electrical Instability in Pentacene Transistors with Mylar and PMMA/Mylar Gate Dielectrics Transferred by Lamination Process

This study deals with electrical instability under bias stress in pentacene-based transistors with gate dielectrics deposited by a lamination process. Mylar film is laminated onto a polyethylene terephthalate (PET) substrate, on which aluminum (Al) gate is deposited, followed by evaporation of organic semiconductor and gold (Au) source/drain contacts in bottom gate top contact configuration (Device 1). In order to compare the influence of the semiconductor/dielectric interface, a second organic transistor (Device 2) which is different from the Device 1 by the deposition of an intermediate layer of polymethyl methacrylate (PMMA) onto the laminated Mylar dielectric and before evaporating pentacene layer is fabricated. The critical device parameters such as threshold voltage (VT), subthreshold slope (S), mobility (μ), onset voltage (Von) and Ion/Ioff ratio have been studied. The results showed that the recorded hysteresis depend on the pentacene morphology. Moreover, after bias stress application, the electrical parameters are highly modified for both devices according to the regimes in which the transistors are operating. In ON state regime, Device 1 showed a pronounced threshold voltage shift associated to charge trapping, while keeping the μ, Ioff current and S minimally affected. Regardless of whether Device 2 exhibited better electrical performances and stability in ON state, we observed a bias stress-induced increase of depletion current and subthreshold slope in subthreshold region, a sign of defect creation. Both devices showed onset voltage shift in opposite direction.

The origin of gate bias stress instability and hysteresis in monolayer WS2 transistors

Due to the ultra-thin nature and moderate carrier mobility,semiconducting two-dimensional(2D)materials have attracted extensive attention for next-generation electronics.However,the gate bias stress instability and hysteresis are always observed in these 2D materials-based transistors that significantly degrade their reliability for practical applications.Herein,the origin of gate bias stress instability and hysteresis for chemical vapor deposited monolayer WS2 transistors are investigated carefully.The transistor performance is found to be strongly affected by the gate bias stress time,sweeping rate and range,and temperature.Based on the systematical study and complementary analysis,charge trapping is determined to be the major contribution for these observed phenomena.Importantly,due to these charge trapping effects,the channel current is observed to decrease with time;hence,a rate equation,considering the charge trapping and time decay effect of current,is proposed and developed to model the phenomena with excellent consistency with experimental data.All these results do not only indicate the validity of the charge trapping model,but also confirm the hysteresis being indeed caused by charge trapping.Evidently,this simple model provides a sufficient explanation for the charge trapping induced gate bias stress instability and hysteresis in monolayer WS2 transistors,which can be also applicable to other kinds of transistors.