A binary-weighted 64-dB programmable gain amplifier with a DCOC and AB-class buffer

This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.

Real-time gradation-expressible amplitude-modulationtype electroholography based on binary-weighted computer-generated hologram

In amplitude-modulation-type electroholography, the binary-weighted computer-generated hologram(BW-CGH) facilitates the gradation-expressible reconstruction of three-dimensional(3 D) objects. To realize real-time gradation-expressible electroholography, we propose an efficient and high-speed method for calculating bit planes consisting of BW-CGHs. The proposed method is implemented on a multiple graphics processing unit(GPU) cluster system comprising 13 GPUs. The proposed BW-CGH method realizes eight-gradation-expressible electroholography at approximately the same calculation speed as that of conventional electroholography based on binary computer-generated holograms. Consequently, we were able to successfully reconstruct a real-time electroholographic 3 D video comprising approximately 180,000 points expressed in eight gradations at 30 frames per second.

Color representation method using RGB color binary-weighted computer-generated holograms

We propose a method for color electroholography using a simple red-green-blue （RGB） gradation representa- tion method without controlling the respective brightness of tile reference RGB-colored lights. The proposed method uses RGB multiple bit planes comprising RGB binary-weighted computer-generated holograms with various light transmittanees. The object points of a given three-dimensional （3D） object are assigned to RGB nmltiple bit planes according to their RGB gradation levels. The RGB multiple bit planes are sequentially displayed in a tim-division-multiplexe- manner. Consequently, the proposed method yields a color gradation representation of a reconstructed 3D object.

A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.

A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA

A novel digitally controlled automatic gain control （AGC） loop circuitry for the global navigation satel- lite system （GNSS） receiver chip is presented. The entire AGC loop contains a programmable gain amplifier （PGA）, an AGC circuit and an analog-to-digital converter （ADC）, which is implemented in a 0.18 μm complementary metal--oxide-semiconductor （CMOS） process and measured. A binary-weighted approach is proposed in the PGA to achieve wide dB-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from -4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm^2 and settles within less than 165 μs while consuming an average current of 1.92 mA at 1.8 V.