Genetic algorithms offer very good performances for solving large optimization problems, especially in the domain of error-correcting codes. However, they have a major drawback related to the time complexity and memor...Genetic algorithms offer very good performances for solving large optimization problems, especially in the domain of error-correcting codes. However, they have a major drawback related to the time complexity and memory occupation when running on a uniprocessor computer. This paper proposes a parallel decoder for linear block codes, using parallel genetic algorithms (PGA). The good performance and time complexity are confirmed by theoretical study and by simulations on BCH(63,30,14) codes over both AWGN and flat Rayleigh fading channels. The simulation results show that the coding gain between parallel and single genetic algorithm is about 0.7 dB at BER = 10﹣5 with only 4 processors.展开更多
直流系统是支撑高比例新能源接入与灵活高效用能的重要技术方向。固态式直流断路器(solid state DC circuit breaker,SSCB)具有开断速度极快、无电弧、寿命长等优点,在中低压直流系统的故障保护中得到广泛应用。随着电力电子器件的发展...直流系统是支撑高比例新能源接入与灵活高效用能的重要技术方向。固态式直流断路器(solid state DC circuit breaker,SSCB)具有开断速度极快、无电弧、寿命长等优点,在中低压直流系统的故障保护中得到广泛应用。随着电力电子器件的发展,固态式直流断路器的拓扑结构、工作性能也在不断进步。为此基于逆阻型集成门极换流晶闸管(intergated gate commutate thyristor,IGCT),提出了一种新型的固态式直流断路器结构及设计方法,通流支路采用逆阻IGCT反并联结构实现双向通流,缓冲支路采用金属氧化物避雷器(metal oxide varistor,MOV)-电容结构来抑制过电压,吸能支路采用MOV吸收系统能量。进一步地,给出了关键元器件的参数设计方法,并验证了有效性;设计了性能良好的重力热管散热器,单个模块散热功率可达700 W;提出了主被动结合的控保策略,提高断路器的保护性能。最后,研制了固态式直流断路器样机,可用于750 V以内的低压直流系统,额定通流可达2 kA,可在百微秒内开断10 kA故障电流,成本低、体积小、高可靠,具有良好的应用前景。展开更多
The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of e...The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.展开更多
The factor having effect on compostie errors of long gage blocks and their control are discussed, and a ba-sis is therefore provided for driprovement of composite accuracy. Calculations and experiments were conduted f...The factor having effect on compostie errors of long gage blocks and their control are discussed, and a ba-sis is therefore provided for driprovement of composite accuracy. Calculations and experiments were conduted for de-formation error resulting for clamp foree and the effect of additional bending moment on parallelism of the measure-ment surfaces. With gage blocks of different length in good conact, clamp force and suppotrs properly chosen, the composite error can be controlled within 0.1μp by reducing or eliminating the effect of additional bending moment on parallelism of measurement surfaces.展开更多
A novel low-complexity iterative receiver for multiuser space frequency block coding (SFBC) system was proposed in this paper. Unlike the conventional linear minimum mean square error (MMSE) detector, which requires m...A novel low-complexity iterative receiver for multiuser space frequency block coding (SFBC) system was proposed in this paper. Unlike the conventional linear minimum mean square error (MMSE) detector, which requires matrix inversion at each iteration, the soft-in soft-out (SISO) detector is simply a parallel interference cancellation (PIC)-matched filter (MF) operation. The probability density function (PDF) of PIC-MF detector output is approximated as Gaussian, whose variance is calculated with a priori information fed back from the channel decoder. With this approximation, the log likelihood ratios (LLRs) of transmitted bits are under-estimated. Then the LLRs are multiplied by a constant factor to achieve a performance gain. The constant factor is optimized according to extrinsic information transfer (EXIT) chart of the SISO detector. Simulation results show that the proposed iterative receiver can significantly improve the system performance and converge to the matched filter bound (MFB) with low computational complexity at high signal-to-noise ratios (SNRs).展开更多
In order to generate an efficient common bitmap in single bitmap block truncation coding(SBBTC)of color images,an improved SBBTC scheme based on weighted plane(W-plane)method and hill climbing algorithm is proposed.Fi...In order to generate an efficient common bitmap in single bitmap block truncation coding(SBBTC)of color images,an improved SBBTC scheme based on weighted plane(W-plane)method and hill climbing algorithm is proposed.Firstly,the incoming color image is partitioned into non-overlapping blocks and each block is encoded using the W-plane method to get an initial common bitmap and quantization values.Then,the hill climbing algorithm is applied to optimize an initial common bitmap and generate a near-optimized common bitmap.Finally,the quantization values are recalculated by the near-optimized common bitmap and the considered color image is reconstructed block by block through the common bitmap and the new quantization values.Since the processing of each image block in SBBTC is independent and identical,parallel computing is applied to reduce the time consumption of this scheme.The simulation results show that the proposed scheme has better visual quality and time consumption than those of the reference SBBTC schemes.展开更多
文摘Genetic algorithms offer very good performances for solving large optimization problems, especially in the domain of error-correcting codes. However, they have a major drawback related to the time complexity and memory occupation when running on a uniprocessor computer. This paper proposes a parallel decoder for linear block codes, using parallel genetic algorithms (PGA). The good performance and time complexity are confirmed by theoretical study and by simulations on BCH(63,30,14) codes over both AWGN and flat Rayleigh fading channels. The simulation results show that the coding gain between parallel and single genetic algorithm is about 0.7 dB at BER = 10﹣5 with only 4 processors.
基金This work is supported in partial by Major State Basic Research Project （No. G19990328, Parallel Computations of the Large-Scale Reservoir Simulation （2003-2004） （Cooperated with China National 0ffshore 0il Corporation）, and National Natural Science Foundation Project （No. 60303020, 2004.1-2006.12）.
基金Supported in part by the "863" Program (No.2003 AA1ZB10)
文摘The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.
文摘The factor having effect on compostie errors of long gage blocks and their control are discussed, and a ba-sis is therefore provided for driprovement of composite accuracy. Calculations and experiments were conduted for de-formation error resulting for clamp foree and the effect of additional bending moment on parallelism of the measure-ment surfaces. With gage blocks of different length in good conact, clamp force and suppotrs properly chosen, the composite error can be controlled within 0.1μp by reducing or eliminating the effect of additional bending moment on parallelism of measurement surfaces.
基金The Science and Technology Committee of Shanghai Municipality ( No 06DZ15013,No03DZ15010)
文摘A novel low-complexity iterative receiver for multiuser space frequency block coding (SFBC) system was proposed in this paper. Unlike the conventional linear minimum mean square error (MMSE) detector, which requires matrix inversion at each iteration, the soft-in soft-out (SISO) detector is simply a parallel interference cancellation (PIC)-matched filter (MF) operation. The probability density function (PDF) of PIC-MF detector output is approximated as Gaussian, whose variance is calculated with a priori information fed back from the channel decoder. With this approximation, the log likelihood ratios (LLRs) of transmitted bits are under-estimated. Then the LLRs are multiplied by a constant factor to achieve a performance gain. The constant factor is optimized according to extrinsic information transfer (EXIT) chart of the SISO detector. Simulation results show that the proposed iterative receiver can significantly improve the system performance and converge to the matched filter bound (MFB) with low computational complexity at high signal-to-noise ratios (SNRs).
基金Supported by the National Natural Science Foundation of China(No.61402537)the Open Fund of Guangxi Key Laboratory of Hybrid Computation and IC Design Analysis(No.HCIC201706)the Sichuan Science and Technology Programme(No.2018GZDZX0041)
文摘In order to generate an efficient common bitmap in single bitmap block truncation coding(SBBTC)of color images,an improved SBBTC scheme based on weighted plane(W-plane)method and hill climbing algorithm is proposed.Firstly,the incoming color image is partitioned into non-overlapping blocks and each block is encoded using the W-plane method to get an initial common bitmap and quantization values.Then,the hill climbing algorithm is applied to optimize an initial common bitmap and generate a near-optimized common bitmap.Finally,the quantization values are recalculated by the near-optimized common bitmap and the considered color image is reconstructed block by block through the common bitmap and the new quantization values.Since the processing of each image block in SBBTC is independent and identical,parallel computing is applied to reduce the time consumption of this scheme.The simulation results show that the proposed scheme has better visual quality and time consumption than those of the reference SBBTC schemes.
