A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity re...A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.展开更多
To achieve sparse sampling on a coded ultrasonic signal,the finite rate of innovation(FRI)sparse sampling technique is proposed on a binary frequency-coded(BFC)ultrasonic signal.A framework of FRI-based sparse samplin...To achieve sparse sampling on a coded ultrasonic signal,the finite rate of innovation(FRI)sparse sampling technique is proposed on a binary frequency-coded(BFC)ultrasonic signal.A framework of FRI-based sparse sampling for an ultrasonic signal pulse is presented.Differences between the pulse and the coded ultrasonic signal are analyzed,and a response mathematical model of the coded ultrasonic signal is established.A time-domain transform algorithm,called the high-order moment method,is applied to obtain a pulse stream signal to assist BFC ultrasonic signal sparse sampling.A sampling of the output signal with a uniform interval is then performed after modulating the pulse stream signal by a sampling kernel.FRI-based sparse sampling is performed using a self-made circuit on an aluminum alloy sample.Experimental results show that the sampling rate reduces to 0.5 MHz,which is at least 12.8 MHz in the Nyquist sampling mode.The echo peak amplitude and the time of flight are estimated from the sparse sampling data with maximum errors of 9.324%and 0.031%,respectively.This research can provide a theoretical basis and practical application reference for reducing the sampling rate and data volume in coded ultrasonic testing.展开更多
A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder ca...A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder cannot distinguish between train charging current and remote short circuit current.This method uses the principle of energy difference to optimize the optimal mode decomposition number k of VMD;the optimal VMD for DC feeder current is decomposed into the intrinsic modal function(IMF)of different frequency bands.The sample entropy algorithm is used to perform feature extraction of each IMF,and then the eigenvalues of the intrinsic modal function of each frequency band of the current signal can be obtained.The recognition feature vector is input into the support vector machine model based on Bayesian hyperparameter optimization for training.After a large number of experimental data are verified,it is found that the optimal VMD_SampEn algorithm to identify the train charging current and remote short circuit current is more accurate than other algorithms.Thus,the algorithm based on optimized VMD_SampEn has certain engineering application value in the fault current identification of the DC traction feeder.展开更多
A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-a...A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.展开更多
文摘A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.
基金The National Natural Science Foundation of China (No.51375217)。
文摘To achieve sparse sampling on a coded ultrasonic signal,the finite rate of innovation(FRI)sparse sampling technique is proposed on a binary frequency-coded(BFC)ultrasonic signal.A framework of FRI-based sparse sampling for an ultrasonic signal pulse is presented.Differences between the pulse and the coded ultrasonic signal are analyzed,and a response mathematical model of the coded ultrasonic signal is established.A time-domain transform algorithm,called the high-order moment method,is applied to obtain a pulse stream signal to assist BFC ultrasonic signal sparse sampling.A sampling of the output signal with a uniform interval is then performed after modulating the pulse stream signal by a sampling kernel.FRI-based sparse sampling is performed using a self-made circuit on an aluminum alloy sample.Experimental results show that the sampling rate reduces to 0.5 MHz,which is at least 12.8 MHz in the Nyquist sampling mode.The echo peak amplitude and the time of flight are estimated from the sparse sampling data with maximum errors of 9.324%and 0.031%,respectively.This research can provide a theoretical basis and practical application reference for reducing the sampling rate and data volume in coded ultrasonic testing.
基金This project supported by The National Natural Science Foundation of China(No.11872253).
文摘A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder cannot distinguish between train charging current and remote short circuit current.This method uses the principle of energy difference to optimize the optimal mode decomposition number k of VMD;the optimal VMD for DC feeder current is decomposed into the intrinsic modal function(IMF)of different frequency bands.The sample entropy algorithm is used to perform feature extraction of each IMF,and then the eigenvalues of the intrinsic modal function of each frequency band of the current signal can be obtained.The recognition feature vector is input into the support vector machine model based on Bayesian hyperparameter optimization for training.After a large number of experimental data are verified,it is found that the optimal VMD_SampEn algorithm to identify the train charging current and remote short circuit current is more accurate than other algorithms.Thus,the algorithm based on optimized VMD_SampEn has certain engineering application value in the fault current identification of the DC traction feeder.
基金supported by the National High Technology Research and Development Program of China(No.2002AA1Z1200)
文摘A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.
