Microarchitects should consider power consumption, together with accuracy, when designing a branch predictor, especially in embedded processors. This paper proposes a power-aware branch predictor, which is based on th...Microarchitects should consider power consumption, together with accuracy, when designing a branch predictor, especially in embedded processors. This paper proposes a power-aware branch predictor, which is based on the gshare predictor, by accessing the BTB （Branch Target Buffer） selectively. To enable the selective access to the BTB, the PHT （Pattern History Table） in the proposed branch predictor is accessed one cycle earlier than the traditional PHT if the program is executed sequentially without branch instructions. As a side effect, two predictions from the PHT are obtained through one access to the PHT, resulting in more power savings. In the proposed branch predictor, if the previous instruction was not a branch and the prediction from the PHT is untaken, the BTB is not accessed to reduce power consumption. If the previous instruction was a branch, the BTB is always accessed, regardless of the prediction from the PHT, to prevent the additional delay/accuracy decrease. The proposed branch predictor reduces the power consumption with little hardware overhead, not incurring additional delay and never harming prediction accuracy. The simulation results show that the proposed branch predictor reduces the power consumption by 29-47%.展开更多
In a modern processor,branch prediction is crucial in effectively exploiting the instruction-level parallelism for high-performance execution.However,recently exposed vulnerabilities reveal the urgency to improve the ...In a modern processor,branch prediction is crucial in effectively exploiting the instruction-level parallelism for high-performance execution.However,recently exposed vulnerabilities reveal the urgency to improve the security of branch predictors.The vital cause of the branch predictor vulnerabilities is that the update strategy of the saturating counter is deterministic.As a fundamental building block in a modern branch predictor,previous studies have paid too much attention to the performance and hardware cost and ignored the security of saturating counter.This leaves attackers with the opportunities to perform side-channel attacks on the branch predictor.This paper focuses on the saturating counter to explore a secure and lightweight design to mitigate branch predictor side-channel attacks.Instead of applying the isolation mechanism to branch predictor resources,we propose a novel probabilistic saturating counter design to confuse the attacker's perception of the victim's behaviour.It changes the conventional deterministic state transition function to a probabilistic state transition function.When a branch is committed,the conventional saturating counter needs to be updated about whether the prediction results are correct or not.While for the probabilistic saturating counter,the branch predictor determines whether the update is performed based on the update probability.The probabilistic saturating counter dramatically reduces the ability of the attacker to spy the saturating counter's state.Our analyses using a cycle-accurate simulator suggest that the proposed mechanism incurs 2.4%performance overhead and hardware cost while providing strong protection.展开更多
文摘Microarchitects should consider power consumption, together with accuracy, when designing a branch predictor, especially in embedded processors. This paper proposes a power-aware branch predictor, which is based on the gshare predictor, by accessing the BTB （Branch Target Buffer） selectively. To enable the selective access to the BTB, the PHT （Pattern History Table） in the proposed branch predictor is accessed one cycle earlier than the traditional PHT if the program is executed sequentially without branch instructions. As a side effect, two predictions from the PHT are obtained through one access to the PHT, resulting in more power savings. In the proposed branch predictor, if the previous instruction was not a branch and the prediction from the PHT is untaken, the BTB is not accessed to reduce power consumption. If the previous instruction was a branch, the BTB is always accessed, regardless of the prediction from the PHT, to prevent the additional delay/accuracy decrease. The proposed branch predictor reduces the power consumption with little hardware overhead, not incurring additional delay and never harming prediction accuracy. The simulation results show that the proposed branch predictor reduces the power consumption by 29-47%.
基金supported by the Strategic Priority Research Program of Chinese Academy of Sciences under Grant No.XDC02010200the National Natural Science Foundation of China under Grant No.62125208.
文摘In a modern processor,branch prediction is crucial in effectively exploiting the instruction-level parallelism for high-performance execution.However,recently exposed vulnerabilities reveal the urgency to improve the security of branch predictors.The vital cause of the branch predictor vulnerabilities is that the update strategy of the saturating counter is deterministic.As a fundamental building block in a modern branch predictor,previous studies have paid too much attention to the performance and hardware cost and ignored the security of saturating counter.This leaves attackers with the opportunities to perform side-channel attacks on the branch predictor.This paper focuses on the saturating counter to explore a secure and lightweight design to mitigate branch predictor side-channel attacks.Instead of applying the isolation mechanism to branch predictor resources,we propose a novel probabilistic saturating counter design to confuse the attacker's perception of the victim's behaviour.It changes the conventional deterministic state transition function to a probabilistic state transition function.When a branch is committed,the conventional saturating counter needs to be updated about whether the prediction results are correct or not.While for the probabilistic saturating counter,the branch predictor determines whether the update is performed based on the update probability.The probabilistic saturating counter dramatically reduces the ability of the attacker to spy the saturating counter's state.Our analyses using a cycle-accurate simulator suggest that the proposed mechanism incurs 2.4%performance overhead and hardware cost while providing strong protection.
