This paper presents the design and implementation of access controller used for Ethernet passive optical network （ EPON）. As a first step to develop an ASIC product, the entire system is designed on a field programm...This paper presents the design and implementation of access controller used for Ethernet passive optical network （ EPON）. As a first step to develop an ASIC product, the entire system is designed on a field programmable gate array （FPGA） with an embedded CPU. To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. Implementations of synchronization, classification, as well as Linux porting are illustrated in detail. The interface between the FPGA and CPU are also presented. Experimental results show that the proposed system can properly function in a relatively low cost FPGA.展开更多
As a promising solution to efficiently achieving fiber to the home （FTTH）, Ethernet passive optical network （EPON） is currently improved to provide intercommunication among customers, together with normal traffic ...As a promising solution to efficiently achieving fiber to the home （FTTH）, Ethernet passive optical network （EPON） is currently improved to provide intercommunication among customers, together with normal traffic delivery, via optical local area network emulation. It is a new research direction and expected to enhance the normal EPON performances. The purpose of this article is to review the state-of -the-art solutions to emulating optical local area networks （OLANs） over EPON. We discuss the major problems involved, e.g., network architecture, control mechanisms, and other potential enhancements. We also outline areas for future researches.展开更多
基金Project supported by Science Foundation of Shanghai Municipal Commission of Science and Technology (Grant No .04dz12045)
文摘This paper presents the design and implementation of access controller used for Ethernet passive optical network （ EPON）. As a first step to develop an ASIC product, the entire system is designed on a field programmable gate array （FPGA） with an embedded CPU. To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. Implementations of synchronization, classification, as well as Linux porting are illustrated in detail. The interface between the FPGA and CPU are also presented. Experimental results show that the proposed system can properly function in a relatively low cost FPGA.
基金the National Science Fund for Distinguished Young Scholars(Grant No.60725104)the National Basic Research Program of China(Grant No.2007CB310706)+2 种基金the National High Technology Research and Development Program of China(Grant Nos.2007AA01Z246 and 2007AA01Z227)the National Natural Science Foundation of China(Grant No.60672045)the Research Fund for the Doctoral Program of Higher Education(Grant No.20060614018)
文摘As a promising solution to efficiently achieving fiber to the home （FTTH）, Ethernet passive optical network （EPON） is currently improved to provide intercommunication among customers, together with normal traffic delivery, via optical local area network emulation. It is a new research direction and expected to enhance the normal EPON performances. The purpose of this article is to review the state-of -the-art solutions to emulating optical local area networks （OLANs） over EPON. We discuss the major problems involved, e.g., network architecture, control mechanisms, and other potential enhancements. We also outline areas for future researches.
