The Sichuan-Tibet transportation corridor is prone to numerous active faults and frequent strong earthquakes.While extensive studies have individually explored the effect of active faults and strong earthquakes on dif...The Sichuan-Tibet transportation corridor is prone to numerous active faults and frequent strong earthquakes.While extensive studies have individually explored the effect of active faults and strong earthquakes on different engineering structures,their combined effect remains unclear.This research employed multiple physical model tests to investigate the dynamic response of various engineering structures,including tunnels,bridges,and embankments,under the simultaneous influence of cumulative earthquakes and stick-slip misalignment of an active fault.The prototype selected for this study was the Kanding No.2 tunnel,which crosses the Yunongxi fault zone within the Sichuan-Tibet transportation corridor.The results demonstrated that the tunnel,bridge,and embankment exhibited amplification in response to the input seismic wave,with the amplification effect gradually decreasing as the input peak ground acceleration(PGA)increased.The PGAs of different engineering structures were weakened by the fault rupture zone.Nevertheless,the misalignment of the active fault may decrease the overall stiffness of the engineering structure,leading to more severe damage,with a small contribution from seismic vibration.Additionally,the seismic vibration effect might be enlarged with the height of the engineering structure,and the tunnel is supposed to have a smaller PGA and lower dynamic earth pressure compared to bridges and embankments in strong earthquake zones crossing active faults.The findings contribute valuable insights for evaluating the dynamic response of various engineering structures crossing an active fault and provide an experimental reference for secure engineering design in the challenging conditions of the Sichuan-Tibet transportation corridor.展开更多
Diagnosing intermittent fault is an important approach to reduce built-in test（BIT） false alarms. Aiming at solving the shortcoming of the present diagnostic method of intermittent fault, and according to the merit ...Diagnosing intermittent fault is an important approach to reduce built-in test（BIT） false alarms. Aiming at solving the shortcoming of the present diagnostic method of intermittent fault, and according to the merit of support vector machines （ SVM） which can be trained with a small-sample, an SVM-based diagnostic model of 3 states that include OK state, intermittent state and faulty state is presented. With the features based on the reflection coefficients of an alarm rate （ AR ） model extracted from small vibration samples, these models are trained to diagnose intermittent faults. The experimental results show that this method can diagnose multiple intermittent faults accurately with small training samples and BIT false alarms are reduced.展开更多
This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator....This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.41825018,41977248,42207219)the Second Tibetan Plateau Scientific Expedition and Research Program(STEP)(Grant No.2019QZKK0904)。
文摘The Sichuan-Tibet transportation corridor is prone to numerous active faults and frequent strong earthquakes.While extensive studies have individually explored the effect of active faults and strong earthquakes on different engineering structures,their combined effect remains unclear.This research employed multiple physical model tests to investigate the dynamic response of various engineering structures,including tunnels,bridges,and embankments,under the simultaneous influence of cumulative earthquakes and stick-slip misalignment of an active fault.The prototype selected for this study was the Kanding No.2 tunnel,which crosses the Yunongxi fault zone within the Sichuan-Tibet transportation corridor.The results demonstrated that the tunnel,bridge,and embankment exhibited amplification in response to the input seismic wave,with the amplification effect gradually decreasing as the input peak ground acceleration(PGA)increased.The PGAs of different engineering structures were weakened by the fault rupture zone.Nevertheless,the misalignment of the active fault may decrease the overall stiffness of the engineering structure,leading to more severe damage,with a small contribution from seismic vibration.Additionally,the seismic vibration effect might be enlarged with the height of the engineering structure,and the tunnel is supposed to have a smaller PGA and lower dynamic earth pressure compared to bridges and embankments in strong earthquake zones crossing active faults.The findings contribute valuable insights for evaluating the dynamic response of various engineering structures crossing an active fault and provide an experimental reference for secure engineering design in the challenging conditions of the Sichuan-Tibet transportation corridor.
文摘Diagnosing intermittent fault is an important approach to reduce built-in test（BIT） false alarms. Aiming at solving the shortcoming of the present diagnostic method of intermittent fault, and according to the merit of support vector machines （ SVM） which can be trained with a small-sample, an SVM-based diagnostic model of 3 states that include OK state, intermittent state and faulty state is presented. With the features based on the reflection coefficients of an alarm rate （ AR ） model extracted from small vibration samples, these models are trained to diagnose intermittent faults. The experimental results show that this method can diagnose multiple intermittent faults accurately with small training samples and BIT false alarms are reduced.
文摘This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.
