A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells,Configurable Logic Blocks(CLBs),and input/output(I/O)pads are all present in every Field Programmable Gate Array(FPGA)structure.The interconnects are formed by the physical paths for connecting the blocks.The combinational and sequential circuits are used in the logic blocks to execute logical functions.The FPGA includes two different tests called interconnect testing and logical testing.Instead of using an additional circuitry,the Built-in-Self-Test(BIST)logic is coded into an FPGA,which is then reconfigured to perform its specific operation after the testing is completed.As a result,additional test circuits for the FPGA board are no longer required.The FPGA BIST has no area overhead or performance reduction issues like conventional BIST.A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation.In this work,the Configurable Logic Blocks(CLBs)of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture.To evaluate the CLBs’capabilities including distributed modes of operation of Random Access Memory(RAM),several types of configurations are created.These setups have the ability to identify 100%stuck-at failures in every CLB.This method is suitable for all phases of FPGA testing and has no overhead or performance cost.

SACSR:a low power BIST method for sequential circuits

A novel built-in-self-test(BIST) method called seeded autonomous cyclic shift register (SACSR) is presented to reduce test power of the sequential circuit. The key idea is to use a pseudorandom pattern generator and several XOR gates to generate seeds that share fewer test vectors. The generated seed is taken XOR operation with a cyclic shift register, and the single input change (SIC) sequence is generated. The proposed scheme is easily implemented and can reduce the switching activities of the circuit under test (CUT) greatly. Experimental results on ISCAS89 benchmarks show that on average more than 63% power reduction can be achieved. It also demonstrates that the generated test vectors attain high fault coverage for stuck-at fault and transition fault coverage with short test length.

Deterministic Circular Self Test Path

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental re- sults on ISCAS’89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.