Sensitivity of Total-Dose Radiation Hardness of SIMOX Buried Oxides to Doses of Nitrogen Implantation into Buried Oxides

In order to improve the total-dose radiation har dness of the buried oxides(BOX) in the structure of separation-by-implanted-oxygen(SIMOX) silicon-on-insulator(SOI),nitrogen ions are implanted into the buried oxides with two different doses,2×10 15 and 3×10 15 cm -2 ,respectively.The experimental results show that the radiation hardness of the buried oxides is very sensitive to the doses of nitrogen implantation for a lower dose of irradiation with a Co-60 source.Despite the small difference between the doses of nitrogen implantation,the nitrogen-implanted 2×10 15 cm -2 BOX has a much higher hardness than the control sample (i.e.the buried oxide without receiving nitrogen implantation) for a total-dose irradiation of 5×104rad(Si),whereas the nitrogen-implanted 3×10 15 cm -2 BOX has a lower hardness than uhe control sample.However,this sensitivity of radiation hardness to the doses of nitrogen implantation reduces with the increasing total-dose of irradiation (from 5×104 to 5×105rad (Si)).The radiation hardness of BOX is characterized by MOS high-frequency (HF) capacitance-voltage (C-V) technique after the top silicon layers are removed.In addition,the abnormal HF C-V curve of the metal-silicon-BOX-silicon(MSOS) structure is observed and explained.

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT （Conv-SJ）, the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop （gce（on）） and an improved tradeoff between gee（on） and turn-off loss （Eoff）, with no breakdown voltage （BV） degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5μm and Nn = Np = 3 × 10^15 cm^-3, the Vce（on） and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 10^18 cm^-3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 10^17 cm^-3, respectively. However, with the same device parameters, the Vce（on） and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc= 1 × 10^18 cm^-3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 ×10^17 cm^-3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator （SOI） high performance lateral double-diffusion metal oxide semiconductor （LDMOS） on a compound buried layer （CBL） with a step buried oxide （SBO CBL SOI） is proposed. The step buried oxide locates holes in the top interface of the upper buried oxide （UBO） layer. Furthermore, holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide （LBO） layer. Consequently, the electric fields in both the thin LBO and the thick UBO are enhanced by these holes, leading to an improved breakdown voltage. The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer. Moreover, SBO CBL SOI can also reduce the self-heating effect.

Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

To harden silicon-on-insulator（SOI） wafers fabricated using separation by implanted oxygen（SIMOX） to total-dose irradiation,the technique of nitrogen implantation into the buried oxide（BOX） layer of SIMOX wafers can be used.However,in this work,it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities,which increased with increasing nitrogen implantation dose.Also,the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing.On the other hand,in our work,it has also been observed that,unlike nitrogen-implanted BOX,all the fluorine-implanted BOX layers show a negative charge density.To obtain the initial charge densities of the BOX layers,the tested samples were fabricated with a metal-BOX-silicon（MBS） structure based on SIMOX wafers for high-frequency capacitance-voltage（C-V） analysis.

A high-voltage SOI MOSFET with a compensation layer on the trenched buried oxide layer

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.

Simulation and Experiment on a Buried-Oxide Trench-Gate Bipolar-Mode JFET

A buried-oxide trench-gate bipolar-mode JFET （BTB-JFET） with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed. Simulations with a resistive load circuit for power loss comparison at high frequency application are performed with 20V-rated power switching devices,including a BTB-JFET,a trench MOSFET （T-MOSFET） generally applied in present industry, and a conventional trench-gate bipolar-mode JFET （TB-JFET） without buried oxide,for the first time. The simulation results indicate that the switching power loss of the normally-on BTB-JFET is improved by 37% and 14% at 1MHz compared to the T-MOSFET and the normally-on TB-JFET, respectively. In order to demonstrate the validity of the simulation, the normally-on TB-JFET and BTB-JFET have been fabricated successfully for the first time, where the buried oxide structure is realized by thermal oxidation. The experimental results show that the Cgd of the BTB-JFET is decreased by 45% from that of the TB-JFET at zero source-drain bias. Compared to the TB-JFET,the switching time and switching power loss of the BTB-JFET decrease approximately by 7. 4% and 11% at 1MHz,respectively. Therefore,the normally-on BTB-JFET could be pointing to a new direction for the R＆D of low volt- age and high frequency switching devices.

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator（SOI） devices. In this new structure, the conventional buried oxide（BOX） in an SOI device is split into two sections： the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer（NPCL）, is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage（BV） is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor（LDMOS） and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance（Ron,sp） is reduced by 69% in comparison to the conventional structure.