In recent years,the exponential proliferation of smart devices with their intelligent applications poses severe challenges on conventional cellular networks.Such challenges can be potentially overcome by integrating c...In recent years,the exponential proliferation of smart devices with their intelligent applications poses severe challenges on conventional cellular networks.Such challenges can be potentially overcome by integrating communication,computing,caching,and control(i4C)technologies.In this survey,we first give a snapshot of different aspects of the i4C,comprising background,motivation,leading technological enablers,potential applications,and use cases.Next,we describe different models of communication,computing,caching,and control(4C)to lay the foundation of the integration approach.We review current stateof-the-art research efforts related to the i4C,focusing on recent trends of both conventional and artificial intelligence(AI)-based integration approaches.We also highlight the need for intelligence in resources integration.Then,we discuss the integration of sensing and communication(ISAC)and classify the integration approaches into various classes.Finally,we propose open challenges and present future research directions for beyond 5G networks,such as 6G.展开更多
Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual...Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.展开更多
基金supported in part by National Key R&D Program of China(2019YFE0196400)Key Research and Development Program of Shaanxi(2022KWZ09)+4 种基金National Natural Science Foundation of China(61771358,61901317,62071352)Fundamental Research Funds for the Central Universities(JB190104)Joint Education Project between China and Central-Eastern European Countries(202005)the 111 Project(B08038)。
文摘In recent years,the exponential proliferation of smart devices with their intelligent applications poses severe challenges on conventional cellular networks.Such challenges can be potentially overcome by integrating communication,computing,caching,and control(i4C)technologies.In this survey,we first give a snapshot of different aspects of the i4C,comprising background,motivation,leading technological enablers,potential applications,and use cases.Next,we describe different models of communication,computing,caching,and control(4C)to lay the foundation of the integration approach.We review current stateof-the-art research efforts related to the i4C,focusing on recent trends of both conventional and artificial intelligence(AI)-based integration approaches.We also highlight the need for intelligence in resources integration.Then,we discuss the integration of sensing and communication(ISAC)and classify the integration approaches into various classes.Finally,we propose open challenges and present future research directions for beyond 5G networks,such as 6G.
文摘Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.
