This paper presents a novel hierarchy cache architecture for the purpose of optimizing IO performance. The main idea of the hierarchy cache is to use a few megabytes of RAM and a pagefile to form a two-level cache arc...This paper presents a novel hierarchy cache architecture for the purpose of optimizing IO performance. The main idea of the hierarchy cache is to use a few megabytes of RAM and a pagefile to form a two-level cache architecture, The pagefile is equivalent to the cache disk in DCD (Disk Caching Disk). The pagefile outperforms data disks, because data are accessed in different units and different ways. Small writes are collected in the RAM cache first, and data will be transferred to the pagefile in large writes later. When the system is idle, it will destage data from the pagefile to data disks. The performance test results show that the hierarchy cache can improve IO performance dramatically for small writes, and the mail server using the hierarchy cache driver can handle transactions about 2.2 times faster than the normal mail server. The hierarchy cache is implemented as a filter driver, so it's transparent to the current Windows 2000/ Windows XP operating system. Key words hierarchy cache - pagefile - small write - disk caching disk - filter driver CLC number TP 311 Foundation item: Supported by the National Natural Science Foundation of China (60273073)Biography: XIE chang-sheng (1945-), male Professor, research direction: storage system, network storage.展开更多
The appearance and wide use of memory hardware bring significant changes to the conventional vertical memory hierarchy that fails to handle contentions for shared hardware resources and expensive data movements.To dea...The appearance and wide use of memory hardware bring significant changes to the conventional vertical memory hierarchy that fails to handle contentions for shared hardware resources and expensive data movements.To deal with these problems,existing schemes have to rely on inefficient scheduling strategies that also cause extra temporal,spatial and bandwidth overheads.Based on the insights that the shared hardware resources trend to be uniformly and hierarchically offered to the requests for co-located applications in memory systems,we present an efficient abstraction of memory hierarchies,called Label,which is used to establish the connection between the application layer and underlying hardware layer.Based on labels,our paper proposes LaMem,a labeled,resource-isolated and cross-tiered memory system by leveraging the way-based partitioning technique for shared resources to guarantee QoS demands of applications,while supporting fast and low-overhead cache repartitioning technique.Besides,we customize LaMem for the learned index that fundamentally replaces storage structures with computation models as a case study to verify the applicability of LaMem.Experimental results demonstrate the efficiency and efficacy of LaMem.展开更多
文摘This paper presents a novel hierarchy cache architecture for the purpose of optimizing IO performance. The main idea of the hierarchy cache is to use a few megabytes of RAM and a pagefile to form a two-level cache architecture, The pagefile is equivalent to the cache disk in DCD (Disk Caching Disk). The pagefile outperforms data disks, because data are accessed in different units and different ways. Small writes are collected in the RAM cache first, and data will be transferred to the pagefile in large writes later. When the system is idle, it will destage data from the pagefile to data disks. The performance test results show that the hierarchy cache can improve IO performance dramatically for small writes, and the mail server using the hierarchy cache driver can handle transactions about 2.2 times faster than the normal mail server. The hierarchy cache is implemented as a filter driver, so it's transparent to the current Windows 2000/ Windows XP operating system. Key words hierarchy cache - pagefile - small write - disk caching disk - filter driver CLC number TP 311 Foundation item: Supported by the National Natural Science Foundation of China (60273073)Biography: XIE chang-sheng (1945-), male Professor, research direction: storage system, network storage.
基金supported in part by National Natural Science Foundation of China(62125202).
文摘The appearance and wide use of memory hardware bring significant changes to the conventional vertical memory hierarchy that fails to handle contentions for shared hardware resources and expensive data movements.To deal with these problems,existing schemes have to rely on inefficient scheduling strategies that also cause extra temporal,spatial and bandwidth overheads.Based on the insights that the shared hardware resources trend to be uniformly and hierarchically offered to the requests for co-located applications in memory systems,we present an efficient abstraction of memory hierarchies,called Label,which is used to establish the connection between the application layer and underlying hardware layer.Based on labels,our paper proposes LaMem,a labeled,resource-isolated and cross-tiered memory system by leveraging the way-based partitioning technique for shared resources to guarantee QoS demands of applications,while supporting fast and low-overhead cache repartitioning technique.Besides,we customize LaMem for the learned index that fundamentally replaces storage structures with computation models as a case study to verify the applicability of LaMem.Experimental results demonstrate the efficiency and efficacy of LaMem.
