为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出...为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出电压经反馈网络传递给反馈端的信号耦合形成由负载电容、负载电流控制的可控零点,可有效提高LDO电路整体的稳定性。此外,电路内部加入了产生动态极点的自适应电流补偿电路以保证次极点不会对环路的相位裕度产生影响。基于0.18μm BCD工艺设计,该电路在0~800 mA的宽负载范围、5 V输入3.3 V输出下相位裕度均高于48°,适用负载电容范围≥1μF,同时该LDO在10~100 kHz的频率范围内输出噪声仅为5.0617μVrms。展开更多
A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique...A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.展开更多
This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, whic...This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 x 550 μm^2 and the quiescent current is 130 μA.展开更多
以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的...以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mV以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.展开更多
基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过...基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过冲状态下开启从LDO输出端到地的快速放电通路,欠冲电压改善电路通过电容耦合获得反映LDO输出电压瞬态变化的采样信号,经反向放大后加速功率管栅极电容放电,进而通过功率管对LDO输出电容充电。仿真结果表明,在TT工艺角下该低压差线性稳压器的空载相位裕度为64.57°,满载相位裕度为62.58°,过冲电压为40 m V,欠冲电压为97.6 m V,线性调整率为0.733‰;负载调整率19μV/m A;电源电压抑制比(PSRR)为-73 d B。展开更多
基金Project supported by the National Natural Science Foundation of China(No60876023)
文摘A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.
文摘This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 x 550 μm^2 and the quiescent current is 130 μA.
文摘以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mV以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.
文摘提出了一种集成于射频芯片的低噪声、快速建立的低压差线性稳压器(LDO)。分析了传统LDO的主要噪声源,在综合考虑芯片的噪声、静态电流和面积后,采用超低频低通滤波器,对LDO的输出噪声进行优化。基于SMIC 0.18μm工艺,采用Cadence软件对电路进行仿真。结果表明,10 Hz到100 k Hz之间的输出积分噪声电压为17μV,建立时间小于18μs,总静态电流为24μA,满足LDO的应用要求。
文摘基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过冲状态下开启从LDO输出端到地的快速放电通路,欠冲电压改善电路通过电容耦合获得反映LDO输出电压瞬态变化的采样信号,经反向放大后加速功率管栅极电容放电,进而通过功率管对LDO输出电容充电。仿真结果表明,在TT工艺角下该低压差线性稳压器的空载相位裕度为64.57°,满载相位裕度为62.58°,过冲电压为40 m V,欠冲电压为97.6 m V,线性调整率为0.733‰;负载调整率19μV/m A;电源电压抑制比(PSRR)为-73 d B。
