Low working loss Si/4H-SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.

Progress of High Voltage Trenched and Implanted 4H-SiC Vertical JFET

A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with trenched and implanted method. Its forward drain current is in excess of 3.12 A (170 W/cm2) with a current gain of ID/IG = 19746 at gate bias VG = 3 V and drain bias VD = 5.5 V. The SiC VJFET device’s related specific on-resistance 54 mΩ·cm2. The BV gain is 250 V with Vg from -10 V to -4 V and is 350 V with Vg from -4 V to -2 V. Self-aligned floating guard rings provide edge termination that blocks 3180V at a gate bias of ?14 V and a drain-current density of 1.53 mA/cm2.

Superjunction 4H-SiC trench-gate IGBT with an integrated clamping PN diode

In this paper,a novel superjunction 4H-silicon carbide(4H-SiC)trench-gate insulated-gate bipolar transistor(IGBT)featuring an integrated clamping PN diode between the P-shield and emitter(TSD-IGBT)is designed and theoretically studied.The heavily doping superjunction layer contributes to a low specific on-resistance,excellent electric field distribution,and quasi-unipolar drift current.The anode of the clamping diode is in floating contact with the P-shield.In the on-state,the potential of the P-shield is raised to the turn-on voltage of the clamping diode,which prevents the hole extraction below the N-type carrier storage layer(NCSL).Additionally,during the turn-off transient,once the clamping diode is turned on,it also promotes an additional hole extraction path.Furthermore,the potential dropped at the semiconductor near the trench-gate oxide is effectively reduced in the off-state.

Comparative study of electrical characteristics for n-type 4H–SiC planar and trench MOS capacitors annealed in ambient NO

The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal-oxide-semiconductor （MOS） capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250 ℃ in NO ambient for above 1 h due to the increasing interface shallow and fast states. These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the （1120） and （1100） faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the （0001） face under the same NO annealing condition. In addition, it is found that Fowler-Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device. However, Poole-Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO2/SiC interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO2/SiC interfaces.