A voltage-controlled chaotic oscillator based on carbon nanotube field-effect transistor for low-power embedded systems

This paper presents a compact and low-power-based discrete-time chaotic oscillator based on a carbon nanotube field-effect transistor implemented using Wong and Deng＇s well-known model. The chaotic circuit is composed of a nonlinear circuit that creates an adjustable chaos map, two sample and hold cells for capture and delay functions, and a voltage shifter that works as a buffer and adjusts the output voltage for feedback. The operation of the chaotic circuit is verified with the SPICE software package, which uses a supply voltage of 0.9 V at a frequency of 20 kHz. The time series, frequency spectra, transitions in phase space, sensitivity with the initial condition diagrams, and bifurcation phenomena are presented. The main advantage of this circuit is that its chaotic signal can be generated while dissipating approximately 7.8 μW of power, making it suitable for embedded systems where many chaos-signal generators are required on a single chip.

Alignment of Nanoscale Single-Walled Carbon Nanotubes Strands

Depositing single-walled carbon nanotubes(SWNTs) with controllable density, pattern and orientation on electrodes presents a challenge in today's research. Here, we report a novel solvent evaporation method to align SWNTs in patterns having nanoscale width and micronscale length. SWNTs suspension has been introduced dropwise onto photoresist resin microchannels; and the capillary force can stretch and align SWNTs into strands with nanoscale width in the microchannels. Then these narrow and long aligned SWNTs patterns were successfully transferred to a pair of gold electrodes with different gaps to fabricate carbon nanotube field-effect transistor(CNTFET). Moreover, the electrical performance of the CNTFET show that the SWNTs strands can bridge different gaps and fabricate good electrical performance CNTFET with ON/OFF ratio around 106. This result suggests a promising and simple strategy for assembling well-aligned SWNTs into CNTFET device with good electrical performance.

Design of Multi-Valued Logic Circuit Using Carbon Nano Tube Field Transistors

The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.

Scaling carbon nanotube complementary transistors to the 5nm gate length and toward the quantum limit

Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,Peking University,Beijing,recently reported that carbon nanotube CMOS FETs were scaled down to the 5nm gate length and presented

Comparative Performance Evaluation of Large FPGAs with CNFET-and CMOS-based Switches in Nanoscale

Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits

Carbon nanotube field-effect transistors(CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing(AC) based error-resilient digital circuits. In this paper, CNTFET technology and the gate diffusion input(GDI) technique are merged, and three new AC-based full adders(FAs) are presented with 6, 6, and 8 transistors, separately. The nondominated sorting based genetic algorithm II(NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits' improvement by about 50% in terms of power-delay-product(PDP) at the cost of area occupation. The Monte Carlo method(MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold(DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit(LSB) parts of more complex arithmetic circuits such as multipliers.

Wafer-scale carbon-based CMOS PDK compatible with siliconbased VLSI design flow

Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,encompassing materials and device technology,have enabled the fabrication of circuits with over 1000 gates,marking carbon-based integrated circuit design as a burgeoning field of research.A critical challenge in the realm of carbon-based very-large-scale integration(VLSI)is the lack of suitable automated design methodologies and infrastructure platforms.In this study,we present the development of a waferscale 3μm carbon-based complementary metal-oxide-semiconductor(CMOS)process design kit(PDK)(3μm-CNTFETs-PDK)compatible with silicon-based Electronic Design Automation(EDA)tools and VLSI circuit design flow.The proposed 3μm-CNTFETs-PDK features a contacted gate pitch(CGP)of 21μm,a gate density of 128 gates/mm^(2),and a transistor density of 554 transistors/mm^(2),with an intrinsic gate delay around 134 ns.Validation of the 3μm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits.Leveraging the carbon-based PDK and a silicon-based design platform,we successfully implemented a complete 64-bit static random-access memory(SRAM)circuit system for the first time,which exhibited timing,power,and area characteristics of clock@10 kHz,122.1μW,3795μm×2810μm.This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow,thereby laying the groundwork for future carbon-based VLSI advancements.