OFDM with Generalized Cascade Index Modulation for Secure Communications

Cascade index modulation(CIM) is a recently proposed improvement of orthogonal frequency division multiplexing with index modulation(OFDM-IM) and achieves better error performance.In CIM, at least two different IM operations construct a super IM operation or achieve new functionality. First, we propose a OFDM with generalized CIM(OFDM-GCIM) scheme to achieve a joint IM of subcarrier selection and multiple-mode(MM)permutations by using a multilevel digital algorithm.Then, two schemes, called double CIM(D-CIM) and multiple-layer CIM(M-CIM), are proposed for secure communication, which combine new IM operation for disrupting the original order of bits and symbols with conventional OFDM-IM, to protect the legitimate users from eavesdropping in the wireless communications. A subcarrier-wise maximum likelihood(ML) detector and a low complexity log-likelihood ratio(LLR) detector are proposed for the legitimate users. A tight upper bound on the bit error rate(BER) of the proposed OFDM-GCIM, D-CIM and MCIM at the legitimate users are derived in closed form by employing the ML criteria detection. Computer simulations and numerical results show that the proposed OFDM-GCIM achieves superior error performance than OFDM-IM, and the error performance at the eavesdroppers demonstrates the security of D-CIM and M-CIM.

Coordinated Capacitor Voltage Balancing Method for Cascaded H-bridge Inverter with Supercapacitor and DC-DC Stage

Cascaded H-bridge inverter(CHBI) with supercapacitors(SCs) and dc-dc stage shows significant promise for medium to high voltage energy storage applications. This paper investigates the voltage balance of capacitors within the CHBI, including both the dc-link capacitors and SCs. Balance control over the dc-link capacitor voltages is realized by the dcdc stage in each submodule(SM), while a hybrid modulation strategy(HMS) is implemented in the H-bridge to balance the SC voltages among the SMs. Meanwhile, the dc-link voltage fluctuations are analyzed under the HMS. A virtual voltage variable is introduced to coordinate the balancing of dc-link capacitor voltages and SC voltages. Compared to the balancing method that solely considers the SC voltages, the presented method reduces the dc-link voltage fluctuations without affecting the voltage balance of SCs. Finally, both simulation and experimental results verify the effectiveness of the presented method.

Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

A Novel Full Differential Feedforward Fourth-Order Bandpass Sigma-Delta Modulator

In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.

COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.

An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers

A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.

Synchronization analysis on cascaded multilevel converters with distributed control

Cascaded multilevel converters built with integrated modules have many advantages such as increased power density,flexible distributed control,multi-functionality,increased reliability and short design cycles.However,the system performance will be affected due to the synchronization errors among each integrated modules.This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance,as well as detailed synchronization implementation.Some valuable conclusions are derived from the theoretical analysis,simulations and experimental results.

THD Analysis of Cascaded H-Bridge Inverter with Fuzzy Logic Controller

In recent days, the multilevel inverter technology is widely applied to domestic and industrial applications for medium voltage conversion. But, the power quality issues of the multilevel inverter limit the usage of much sensitive equipment like medical instruments. The lower distortion level of the output voltage and current can generate a quality sinusoidal output voltage in inverters and they can be used for many applications. The harmonics can cause major problems in equipments due to the nonlinear loads connected with the power system. So, it is necessary to minimize the losses to raise its overall efficiency. In this paper, a new topology of seven level asymmetrical cascaded H-bridge multilevel inverter with a Fuzzy logic controller had been implemented to reduce the Total Harmonic Distortion (THD) and to improve the overall performance of the inverter. The proposed model is well suited for use with a solar PV application. In this topology, only six IGBT switches are used with three different voltage ratings of PV modules (1:2:4). The lower number of semiconductor switches leads to minimizing overall di/dt ratings and voltage stress on each switches and switching losses. The gate pulses generated by Sinusoidal Pulse Width Modulation (SPWM) technique with a Fuzzy logic controller are also introduced. A buck-boost converter is used to maintain the constant PV voltage level integrated by an MPPT technique followed by Perturb and Observer algorithm is also implemented. The MPPT is used to harness the maximum power of solar radiations under its various climatic conditions. The new topology is evaluated by a Matlab/Simulink model and compared with a hardware model. The results proved that the THD achieved by this topology is 1.66% and realized that it meets the IEEE harmonic standards.

采用Mash2-1架构的高精度Sigma-Delta ADC设计

鉴于模数转换器(ADC)在芯片和混合信号处理领域举足轻重的作用,为探索进一步提高模数转换器精度的可能性,满足当今应用系统对模数转换精度的新需求,设计一款基于Mash2-1级联架构的sigma-delta ADC。设计采用TSMC 180 nm CMOS工艺,在完成调制器电路的同时,使用Verilog代码方式实现了配套的误差消除以及数字抽取滤波器。对调制器进行了建模及非理想因素的分析,并通过使用斩波调制技术等手段对电路的非理想性进行优化。经仿真验证,结果表明,本设计在3.3 V电源、27℃工作环境、TT典型工艺条件下,表现出优异的信噪比,总谐波失真等性能指标也较理想,适用于高精度、低失真的应用场合。

基于改进Cascade RCNN的输电线路防振锤脱落检测方法

无人机巡检输电线路时,因拍摄角度和距离问题,容易出现被输电线遮挡和远距离拍摄的防振锤脱落目标,导致目标特征被遮挡且分辨率较低,且部分防振锤出现滑移现象,导致目标识别准确率降低。针对以上问题,提出一种基于改进Cascade RCNN的防振锤脱落检测网络。第一,设计了对比学习网络,将正负样本与真实样本的特征进行对比学习,利用对比损失函数训练网络,使其能更加关注到被遮挡的防振锤脱落目标,提升其特征提取能力;第二,进行了分类器增强操作,筛选出网络级联结构中回归效果较好的感兴趣区域并送入最后的分类回归队列中,提高了分类器的分类能力,进而提升检测目标的分类分数;第三,设计了并行注意力机制模块,整合网络提取的特征,增大关键特征的权重,使网络关注到图像中更关键的区域;在特征金字塔中,将双线性插值方法代替为反卷积,提升特征还原能力。经交叉验证实验结果表明,改进后的模型召回率、精确率和平均精度达到了97.5%,91.0%和92.0%,相比基线模型分别提高了6.9%,28.4%和8.0%。

Analysis and design of sigma-delta interface circuit for quartz flexural pendulum accelerometer

For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor （SC） sigma-delta modulator （SDM） is proposed. Based on the principle and the topology structure of the SDMs, the influence of oversampling ratio, bits of an internal quantizer and the cascaded structure on weak signal detecting precision is analyzed, and an ideal low-distortion SDM with a second-order 1-bit structure satisfying the high- resolution interface circuit of an accelerometer is designed. With the research on non-idealities of each SDM block in the SC circuit implementation and their impacts on power consumption, the realized parameters of low-power SDMs based on different bandwidths are devised and the power consumption of each SDM is estimated. Time-domain behavioral simulation is explored based on Simulink. The results demonstrate that a 21- bit resolution of the designed SDMs can be achieved on the premise of low power, and the parameters for the circuit implementation can be directed to the transistor-level circuit design.

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

A 16bit 96kHz Chopper-Stabilized Sigma-Delta ADC

A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilization is applied to the first integrator to eliminate the 1/f noise.A low-power,area-efficient decimator is used,which includes a poly-phase comb-filter and a wave-digital-filter.The converter achieves a 92dB dynamic range over the 96kHz audio band.This single chip occupies 2.68mm2 in a 0.18μm six-metal CMOS process and dissipates only 15.5mW power.

三阶级联Sigma-Delta调制器设计

介绍2-1级联的三阶调制器设计结构,讨论信号比例系数、积分增益系数和电路非理想特性对调制器系统的性能影响;运用SIMULINK对调制器建模并仿真,模型中考虑开关电容积分器的非理想因素对整个调制器的影响,并通过调整信号比例和积分增益系数来确定调制器性能和电路要求。当采样率为125和时钟频率2.50MHz时,该模型结构得到93dB的信噪失真比,可应用于实际的电路系统。

一种新型的级联Sigma-Delta调制器的建模设计

文章提出了一种新型的级联Sigma-Delta调制器。传统的级联Sigma-Delta调制器需要数字逻辑部分来抵消第1级的量化噪声,数字部分与模拟电路之间的不完全匹配将造成误差泄露。为此,有学者提出了Sturdy-MASH(SMASH)Sigma-Delta调制器以及DNC-SMASH Sigma-Delta调制器来解决误差泄露问题。该文基于上述方法对二阶Sigma-Delta调制器进行了改进,提出了一种新型的两级级联结构,使二阶调制器和额外的一位量化器级联,以此提高调制器的噪声整形。文中分析了非理想因素包括积分器中运放的有限直流增益对信噪比的影响。采用Matlab Simulink对该调制器进行建模仿真,结果表明,在过采样率为256、输入信号带宽为20 kHz时,调制器的信噪比达到114.4 dB,精度高达18.16位。

Highly-sensitive NO,NO2,and NH3 measurements with an open-multipass cell based on mid-infrared wavelength modulation spectroscopy

A compact prototype based on mid-infrared wavelength modulation spectroscopy（WMS）is developed for the simul-taneous monitoring of NO,NO2,and NH3 in the urban area.Three quantum cascade lasers（QCLs）with central frequencies around 1900.0 cm^-1,1600.0 cm^-1,and 1103.4 cm^-1are used for NO,NO2,and NH3detections,respectively,by timedivision multiplex.An open-path multi-pass cell of 60-m optical path length is applied to the instrument for high sensitivity and reducing the response time to less than 1 s.The prototype achieves a sub-ppb detection limit for all the three target gases with an average time of about 100 s.The instrument is installed in the Jiangsu environmental monitoring center to conduct performance tests on ambient air.Continuous 24-hour measurements show good agreement with the results of a reference instrument based on the chemiluminescence technique.

A 3V 5.88mW 13b 400kHz Sigma-Delta Modulator with 84dB Dynamic Range

This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.

四阶级联Sigma-Delta转换器设计

在当今的DSP系统中,作为联系模拟世界与强大的数字领域的桥梁,ADC演了重要的角色。由于Sigma-Delta ADC很好地折衷了转换器的速度和精度,因此成为了用于通信系统中ADC的极佳选择。本文采用了2-1-1结构实现4阶调制器,设计了一个全差分增益提高Telescopic运算放大器,用于第一级积分器。采用了0.6μmN-Well CMOS工艺下加以模拟,电源电压为3v时,功耗为39Mw,调制器的信噪比达到87.3DB.

Atmospheric N2O gas detection based on an inter-band cascade laser around 3.939 μm

N2O is a significant atmospheric greenhouse gas that contributes to global warming and climate change.In this work,the high sensitivity detection of atmospheric N2O is achieved using wavelength modulation spectroscopy(WMS)with an inter-band cascade laser operating around 3.939μm.A Lab VIEW-based software signal generator and software lock-in amplifiers are designed to simplify the system.In order to eliminate the interference from water vapor,the detection was performed at a pressure of 0.1 atm(1 atm=1.01325×10^5 Pa)and a drying tube was added to the system.To improve the system performance for long term detection,a novel frequency locking method and 2 f/1 f calibration-free method were employed to lock the laser frequency and calibrate the power fluctuations,respectively.The Allan deviation analysis of the results indicates a detection limit of^20 ppb(1 ppb=1.81205μg/m3)for a 1 s integration time,and the optimal detection limit is^5 ppb for a 40-s integration time.

Spectroscopy system based on a single quantum cascade laser for simultaneous detection of CO and CO_2

A quantum cascade laser（QCL） based system for simultaneous detection of CO and CO_2 is developed.The QCL can scan over two neighboring CO（2055.40 cm^（-1）） and CO_2（2055.16 cm^（-1）） lines with a single current scan.The wavelength modulation spectroscopy（ f = 20 k Hz） is utilized to enhance the signal-to-noise ratio.A white cell with an effective optical path length of 74 m is used.The calibration of the sensor is performed and minimum detection limits of 1.3 ppb（1 × 10^（-9））for CO and 0.44 ppm（1 × 10^（-6）） for CO_2 are achieved.