A data acquisition system （DAS） to implement high-speed, real-time and multi-channel data acquisition and store is presented. The control of the system is implemented by the combination of complex programable logic ...A data acquisition system （DAS） to implement high-speed, real-time and multi-channel data acquisition and store is presented. The control of the system is implemented by the combination of complex programable logic device （CPLD） and digital signal processing （DSP）, the bulk buffer of the system is implemented by the combination of CPLD, DSP, and synchronous dynamic random access memory （SDRAM）, and the data transfer is implemented by the combination of DSP, first in first out （FIFO）, universal serial bus （USB） and USB hub. The system could not only work independently in single-channel mode, but also implement high-speed real-time multi-channel data acquisition system （MCDAS） by the combination of multiple single-channels. The sampling rate and data storage capacity of each channel could reach up to 100 million sampiing per second and 256 MB respectively.展开更多
NOC（network-on-chip）设计中,最重要的问题是如何提高NOC的性能并减小延时。通讯网络中的的节点结构对NOC的性能和延时有着重要影响。而其中通讯节点虚拟通道的buffer深度尤为关键。通过NIRGAM（NOC Interconnect Routing and Ap plic...NOC（network-on-chip）设计中,最重要的问题是如何提高NOC的性能并减小延时。通讯网络中的的节点结构对NOC的性能和延时有着重要影响。而其中通讯节点虚拟通道的buffer深度尤为关键。通过NIRGAM（NOC Interconnect Routing and Ap plication Modeling）仿真器对一个基于XY路由算法的3×4的2D-Mesh结构NOC进行研究。分析结果表明：通讯节点虚拟通道的输入FIFO（First-In-Fist-Out）的buffer深度大于等于6时,NOC即得到优化。而该buffer深度为6到16时,优化效果并不理想。展开更多
文摘A data acquisition system （DAS） to implement high-speed, real-time and multi-channel data acquisition and store is presented. The control of the system is implemented by the combination of complex programable logic device （CPLD） and digital signal processing （DSP）, the bulk buffer of the system is implemented by the combination of CPLD, DSP, and synchronous dynamic random access memory （SDRAM）, and the data transfer is implemented by the combination of DSP, first in first out （FIFO）, universal serial bus （USB） and USB hub. The system could not only work independently in single-channel mode, but also implement high-speed real-time multi-channel data acquisition system （MCDAS） by the combination of multiple single-channels. The sampling rate and data storage capacity of each channel could reach up to 100 million sampiing per second and 256 MB respectively.
文摘NOC（network-on-chip）设计中,最重要的问题是如何提高NOC的性能并减小延时。通讯网络中的的节点结构对NOC的性能和延时有着重要影响。而其中通讯节点虚拟通道的buffer深度尤为关键。通过NIRGAM（NOC Interconnect Routing and Ap plication Modeling）仿真器对一个基于XY路由算法的3×4的2D-Mesh结构NOC进行研究。分析结果表明：通讯节点虚拟通道的输入FIFO（First-In-Fist-Out）的buffer深度大于等于6时,NOC即得到优化。而该buffer深度为6到16时,优化效果并不理想。
