This article describes the effective channel length degradation under hot carrier stressing. The extraction is based on the IDs-Vcs characteristics by maximum transconductance （maximum slope of IDs ＆ VGS） in the li...This article describes the effective channel length degradation under hot carrier stressing. The extraction is based on the IDs-Vcs characteristics by maximum transconductance （maximum slope of IDs ＆ VGS） in the linear region. The transconductance characteristics are determine for the several devices of difference drawn channel length. The effective channel length of submicron LDD （Lightly Doped Drain） NMOSFETs （Metal Oxide Semiconductor Field Effect Transistor） under hot carrier stressing was measured at the stress time varying from zero to 10,000 seconds. It is shown that the effective channel length was increased with time. This is caused by charges trapping in the oxide during stress. The increased of effective channel length （△Leff） is seem to be increased sharply as the gate channel length is decrease.展开更多
针对具有poly-Si1-x Ge x栅的应变Si Ge p型金属氧化物半导体场效应晶体管(PMOSFET),研究了其垂直电势与电场分布,建立了考虑栅耗尽的poly-Si1-x Ge x栅情况下该器件的等效栅氧化层厚度模型,并利用该模型分析了poly-Si1-x Ge x栅及应变S...针对具有poly-Si1-x Ge x栅的应变Si Ge p型金属氧化物半导体场效应晶体管(PMOSFET),研究了其垂直电势与电场分布,建立了考虑栅耗尽的poly-Si1-x Ge x栅情况下该器件的等效栅氧化层厚度模型,并利用该模型分析了poly-Si1-x Ge x栅及应变Si Ge层中Ge组分对等效氧化层厚度的影响.研究了应变Si Ge PMOSFET热载流子产生的机理及其对器件性能的影响,以及引起应变Si Ge PMOSFET阈值电压漂移的机理,并建立了该器件阈值电压漂移模型,揭示了器件阈值电压漂移随电应力施加时间、栅极电压、polySi1-x Ge x栅及应变Si Ge层中Ge组分的变化关系.并在此基础上进行了实验验证,在电应力施加10000 s时,阈值电压漂移0.032 V,与模拟结果基本一致,为应变Si Ge PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础.展开更多
For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is deve...For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is developed.We investigate the improved short channel effect（SCE）,hot carrier effect（HCE）,drain-induced barrier-lowering（DIBL） and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a＂rollup＂in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.展开更多
文摘This article describes the effective channel length degradation under hot carrier stressing. The extraction is based on the IDs-Vcs characteristics by maximum transconductance （maximum slope of IDs ＆ VGS） in the linear region. The transconductance characteristics are determine for the several devices of difference drawn channel length. The effective channel length of submicron LDD （Lightly Doped Drain） NMOSFETs （Metal Oxide Semiconductor Field Effect Transistor） under hot carrier stressing was measured at the stress time varying from zero to 10,000 seconds. It is shown that the effective channel length was increased with time. This is caused by charges trapping in the oxide during stress. The increased of effective channel length （△Leff） is seem to be increased sharply as the gate channel length is decrease.
文摘针对具有poly-Si1-x Ge x栅的应变Si Ge p型金属氧化物半导体场效应晶体管(PMOSFET),研究了其垂直电势与电场分布,建立了考虑栅耗尽的poly-Si1-x Ge x栅情况下该器件的等效栅氧化层厚度模型,并利用该模型分析了poly-Si1-x Ge x栅及应变Si Ge层中Ge组分对等效氧化层厚度的影响.研究了应变Si Ge PMOSFET热载流子产生的机理及其对器件性能的影响,以及引起应变Si Ge PMOSFET阈值电压漂移的机理,并建立了该器件阈值电压漂移模型,揭示了器件阈值电压漂移随电应力施加时间、栅极电压、polySi1-x Ge x栅及应变Si Ge层中Ge组分的变化关系.并在此基础上进行了实验验证,在电应力施加10000 s时,阈值电压漂移0.032 V,与模拟结果基本一致,为应变Si Ge PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础.
基金Project supported by the National Natural Science Foundation of China(Nos.60976068,60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China Program(No.708083)the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.200807010010).
文摘For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is developed.We investigate the improved short channel effect（SCE）,hot carrier effect（HCE）,drain-induced barrier-lowering（DIBL） and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a＂rollup＂in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.
