Complementary charge islands structure for a high voltage device of partial-SOI

A new partial-SOI （PSOI） high voltage device structure named CNCI PSOI （complementary n＋-charge islands PSOI） is proposed. CNCI PSOI is characterized by equidistant high concentration n＋-regions on the top and bottom interfaces of a dielectric buried layer of a PSOI device. When a high voltage is applied to the device, complementary holes and electron islands are formed on the two n＋-regions on the top and bottom interfaces, therefore effectively enhancing the electric field of the dielectric buried layer （E1 and increasing the breakdown voltage （BV）, alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CNCI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. BV and EI of the CNCI PSOI LDMOS increase to 5 91 V and 512 V/μm from 216 V and 81.4 Vμm of the conventional PSOI with a lower SHE, respectively. The influence of structure parameters on the device characteristics is analyzed for the proposed device in detail.

Thin silicon layer SOI power device with linearly-distance fixed charge islands

A new high-voltage LDMOS with linearly-distanced fixed charge islands is proposed （LFI LDMOS）. A lot of linearly-distanced fixed charge islands are introduced by implanting the Cs or I ion into the buried oxide layer and dynamic holes are attracted and accumulated, which is crucial to enhance the electric field of the buried oxide and the vertical breakdown voltage. The surface electric field is improved by increasing the distance between two adjacent fixed charge islands from source to drain, which lead to the higher concentration of the drift region and a lower on-resistance. The numerical results indicate that the breakdown voltage of 500 V with Ld = 45μm is obtained in the proposed device in comparison to 209 V of conventional LDMOS, while maintaining low on- resistance.

A novel complementary N^+-charge island SOI high voltage device

A new complementary interface charge island structure of SOI high voltage device（CNI SOI） and its model are presented.CNI SOI is characterized by equidistant high concentration n＋-regions on the top and bottom interfaces of dielectric buried layers.When a high voltage is applied to the device,complementary hole and electron islands are formed on the two n＋-regions on the top and bottom interfaces.The introduced interface charges effectively increase the electric field of the dielectric buried layer（EI） and reduce the electric field of the silicon layer（ES）,which result in a high breakdown voltage（BV）.The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI.EI=731 V/μm and BV=750 V are obtained by 2D simulation on a 1-μm-thick dielectric layer and 5-μm-thick top silicon layer.Moreover,enhanced field EI and reduced field ES by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm,respectively.

A new SOI high voltage device based on E-SIMOX substrate

A new NI （n^＋ charge islands） high voltage device structure based on E-SIMOX （epitaxy-the separation by implantation of oxygen） substrate is proposed. It is characterized by equidistant high concentration n＋-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field （Ev） are located in the spacing of two neighboring n^＋-regions on the interface by the force from lateral electric field （EL） and the compositive operation of Coulomb＇s forces with the ionized donors in the undepleted n^＋-regions. This effectively enhances the electric field of dielectric buried layer （EI） and increases breakdown voltage （VB）. An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology （E-SIMOX）.