一种使Charge-pump的输出电压稳定的时钟电路

随着工艺的提高和电源电压的降低,需要能够在低电压下工作的电路。该文介绍了一种能在1.8V电压下工作的时钟产生器。它的频率随着电源电压的增大而减小,随着温度的升高而增大,并能抑制制程的偏差对频率产生的影响。从而使Charge-pump的输出电压稳定。

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Stability Analysis of CPLL with Loop Delay

In this paper,a discrete-time analysis of the third-order charge-pump based phase-locked loops (CPLLs) is presented in the presence of loop delay.The z-domain analysis of the closed-loop transfer function is derived and compared with the traditional s-domain method.The simulation results under SPECTRE show that,due to the sampling nature of CPLL,the traditional s-domain analysis is unable to predict its jitter peaking accurately,especially when the loop delay is taken into consideration.The impact of loop delay on the stability of the third-order CPLL system is further analyzed based on the proposed way.The stability limit of the wide bandwidth CPLL with loop delay is calculated.The circuit simulation results agree well with mathematical analysis.

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS （SG-NLDMOS） transistors are investigated in detail by a DC voltage stress experiment, a TCAD simulation and a charge pumping test. For different stress conditions, degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented. Then the effect of various doses of n-type drain drift （NDD） region implant on Ron degradation is investigated. Experimental results show that a lower NDD dosage can reduce the hot-carrier induced Ron degradation effectively, which is different from uniform gate oxide NLDMOS （UG-NLDMOS） transistors.

Off-state avalanche breakdown induced degradation in 20 V NLDMOS devices

Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented.A constant current pulse stressing test is applied to the device.Two different degradation mechanisms are identified by analysis of electrical data,technology computer-aided design（TCAD） simulations and charge pumping measurements.The first mechanism is attributed to positive oxide-trapped charges in the N-type drift region,and the second one is due to decreased electron mobility upon interface state formation in the drift region.Both of the mechanisms are enhanced with increasing avalanche breakdown current.

An area-saving dual-path loop filter for low-voltage integrated phase-locked loops

This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.