A p-type low-temperature poly-Si thin film transistors（LTPS TFTs） integrated gate driver using 2 nonoverlapped clocks is proposed.This gate driver features charge-sharing structure to turn off buffer TFT and suppres...A p-type low-temperature poly-Si thin film transistors（LTPS TFTs） integrated gate driver using 2 nonoverlapped clocks is proposed.This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects.It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period.The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases.The proposed gate driver shows a simple circuit,as only 6 TFTs and 1 capacitor are used for single-stage,and the buffer TFT is used for both pulling-down and pulling-up of output electrode.Feasibility of the proposed gate driver is proven through detailed analyses.Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than0.8 pF,and pulse of gate driver outputs can be reduced to 5μs.The proposed gate driver can still function properly with positive V（TH）shift within 0.4 V and negative V（TH） shift within-1.2 V and it is robust and promising for high-resolution display.展开更多
A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high searc...A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high search speed.Pre-layout simulation results show a 75.9% energy-delay-product（EDP） reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method.Based on this technique,a test-chip of 64-word × 144-bit ternary CAM（TCAM） is implemented using a 0.18-μm 1.8-V CMOS process,achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs.展开更多
This paper presents a design of 14-bit 80 Msample/s pipelined ADC implemented in 0.35μm CMOS. A charge-sharing correction is proposed to remove the signal-dependent charge-injection,together with a low-jitter clock c...This paper presents a design of 14-bit 80 Msample/s pipelined ADC implemented in 0.35μm CMOS. A charge-sharing correction is proposed to remove the signal-dependent charge-injection,together with a low-jitter clock circuit,guaranteeing the high dynamic performance for the ADC.A scheme of capacitor-switching and a symmetrical layout technique minimizes capacitor mismatch,ensuring the overall linearity.The measured results show that the calibration-free ADC achieves an effective number of bits of 11.6-bit,spurious free dynamic range （SFDR） of 84.8 dB,signal-to-noise-and-distortion ratio（SNDR） of 72 dB,differential nonlinearity of＋0.63/—0.6 LSB and integrated nonlinearity of＋ 1.3/-0.9 LSB at 36.7 MHz input and maintains over 75 dB SFDR and 59 dB SNDR up to 200 MHz.展开更多
基金Project supported by the Science and Technology Project of Hunan Province,China(No.2015JC3401)
文摘A p-type low-temperature poly-Si thin film transistors（LTPS TFTs） integrated gate driver using 2 nonoverlapped clocks is proposed.This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects.It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period.The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases.The proposed gate driver shows a simple circuit,as only 6 TFTs and 1 capacitor are used for single-stage,and the buffer TFT is used for both pulling-down and pulling-up of output electrode.Feasibility of the proposed gate driver is proven through detailed analyses.Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than0.8 pF,and pulse of gate driver outputs can be reduced to 5μs.The proposed gate driver can still function properly with positive V（TH）shift within 0.4 V and negative V（TH） shift within-1.2 V and it is robust and promising for high-resolution display.
文摘A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high search speed.Pre-layout simulation results show a 75.9% energy-delay-product（EDP） reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method.Based on this technique,a test-chip of 64-word × 144-bit ternary CAM（TCAM） is implemented using a 0.18-μm 1.8-V CMOS process,achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs.
文摘This paper presents a design of 14-bit 80 Msample/s pipelined ADC implemented in 0.35μm CMOS. A charge-sharing correction is proposed to remove the signal-dependent charge-injection,together with a low-jitter clock circuit,guaranteeing the high dynamic performance for the ADC.A scheme of capacitor-switching and a symmetrical layout technique minimizes capacitor mismatch,ensuring the overall linearity.The measured results show that the calibration-free ADC achieves an effective number of bits of 11.6-bit,spurious free dynamic range （SFDR） of 84.8 dB,signal-to-noise-and-distortion ratio（SNDR） of 72 dB,differential nonlinearity of＋0.63/—0.6 LSB and integrated nonlinearity of＋ 1.3/-0.9 LSB at 36.7 MHz input and maintains over 75 dB SFDR and 59 dB SNDR up to 200 MHz.
