The space charge effect (SCE) of static induction transistor (SIT) that occurs in high current region is systematically studied.The I V equations are deduced and well agree with experimental results.Two kinds of ...The space charge effect (SCE) of static induction transistor (SIT) that occurs in high current region is systematically studied.The I V equations are deduced and well agree with experimental results.Two kinds of barriers are presented in SIT,corresponding to channel voltage barrier control (CVBC) mechanism and space charge limited control (SCLC) mechanism respectively.With the increase of drain voltage,the gradual transferring of operational mechanism from CVBC to SCLC is demonstrated.It points out that CVBC mechanism and its contest relationship with space charge barrier makes the SIT distinctly differentiated from JFET and triode devices,etc.The contest relationship of the two potential barriers also results in three different working regions,which are distinctly marked and analyzed.Furthermore,the extreme importance of grid voltage on SCE is illustrated.展开更多
Spatio-temporal distribution of individual filament in a square superlattice pattern, which consists of large and small spots （filaments）, is studied in atmospheric dielectric barrier discharges. The spatial distrib...Spatio-temporal distribution of individual filament in a square superlattice pattern, which consists of large and small spots （filaments）, is studied in atmospheric dielectric barrier discharges. The spatial distributions of the two discharges for individual large filament along the direction perpendicular to the electrode are estimated by the distributions of light signals along the electrode. It is found that the discharge at the rising edge of the applied voltage is with a wider column, weaker current, and longer current pulse duration in comparison with that at the falling edge展开更多
The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardl...The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.展开更多
文摘The space charge effect (SCE) of static induction transistor (SIT) that occurs in high current region is systematically studied.The I V equations are deduced and well agree with experimental results.Two kinds of barriers are presented in SIT,corresponding to channel voltage barrier control (CVBC) mechanism and space charge limited control (SCLC) mechanism respectively.With the increase of drain voltage,the gradual transferring of operational mechanism from CVBC to SCLC is demonstrated.It points out that CVBC mechanism and its contest relationship with space charge barrier makes the SIT distinctly differentiated from JFET and triode devices,etc.The contest relationship of the two potential barriers also results in three different working regions,which are distinctly marked and analyzed.Furthermore,the extreme importance of grid voltage on SCE is illustrated.
基金supported by National Natural Science Foundation of China (No.10775037)Natural Science Foundation of Hebei Province of China (No.A2008000564) Natural Science Foundation of Hebei University 2008Q17, China
文摘Spatio-temporal distribution of individual filament in a square superlattice pattern, which consists of large and small spots （filaments）, is studied in atmospheric dielectric barrier discharges. The spatial distributions of the two discharges for individual large filament along the direction perpendicular to the electrode are estimated by the distributions of light signals along the electrode. It is found that the discharge at the rising edge of the applied voltage is with a wider column, weaker current, and longer current pulse duration in comparison with that at the falling edge
基金Project supported by the National Defense Pre-Research Foundation of China(No.51311050301095)
文摘The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.
