In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loo...In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.展开更多
A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technolo...A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor (CMOS) mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.展开更多
We numerically investigate the valley-polarized current in symmetric and asymmetric zigzag graphene nanoribbons(ZGNRs) by the adiabatic pump, and the effect of spatial symmetry is considered by introducing different p...We numerically investigate the valley-polarized current in symmetric and asymmetric zigzag graphene nanoribbons(ZGNRs) by the adiabatic pump, and the effect of spatial symmetry is considered by introducing different pumping regions. It is found that pumping potentials with the symmetry Vp(x,y) = Vp(-x,y)can generate the largest valleypolarized current. The valley-polarized currents I13~L with the pumping potential symmetry Vp(x,y) =Vp(x,-y,) and I14~L with Vp(x,y) = Vp(-x,-y) of symmetric ZGNRs are much smaller than those of asymmetric ZGNRs. We also find I13~L and I14~L of symmetric ZGNRs decrease and increase with the increasing pumping amplitude, respectively. Moreover, the dephasing effect from the electron-phonon coupling within the Buttiker dephasing scheme is introduced. The valley-polarized current of the symmetric ZGNRs with Vp(x,y)= Vp(x,-y) increases with the increase of the dephasing strength while that with Vp(x,y) = Vp(-x,-y) decreases as the dephasing strength increases.展开更多
A self-balanced charge pump (CP) with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor...A self-balanced charge pump (CP) with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor (CMOS) process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector (PFD) was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.展开更多
We report a theoretical study of pumped spin currents in a silicene-based pump device, where two time-dependent staggered potentials are introduced through the perpendicular electric fields and a magnetic insulator is...We report a theoretical study of pumped spin currents in a silicene-based pump device, where two time-dependent staggered potentials are introduced through the perpendicular electric fields and a magnetic insulator is considered in between the two pumping potentials to magnetize the Dirac electrons. It is shown that giant spin currents can be generated in the pump device because the pumping can be optimal for each transport mode, the pumping current is quantized. By controlling the relevant parameters of the device, both pure spin currents and fully spin-polarized currents can be obtained.Our results may shed a new light on the generation of pumped spin currents in Dirac-electron systems.展开更多
A 3.5 times PLL clock frequency multiplier for low voltage different signal (LVDS) driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator (...A 3.5 times PLL clock frequency multiplier for low voltage different signal (LVDS) driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator (VCO) is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .展开更多
In wireless sensor network (WSN), the communication node is the heart of the whole system. Negative bias temperature instability (NBTI) is becoming one of the most important factors that decide the life time of no...In wireless sensor network (WSN), the communication node is the heart of the whole system. Negative bias temperature instability (NBTI) is becoming one of the most important factors that decide the life time of node chips, especially with the feature size declining. In this paper, the NBTI impact on the front-end circuits in the WSN nodes is studied, such as voltage-controlled oscillator (VCO), charge pump (CP), low noise amplifier (LNA), and even the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. It is shown that the phase noise of the VCO will be deteriorated, the current mismatch of the CP and the noise figure of the LNA will both be increased, and the sensitivity and the adjacent channel selectivity (ACS) will be depressed by NBTI. The conclusions are proved by simulation results using HJTC 0.18 μm technology.展开更多
A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk o...A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.展开更多
A fully-differential charge pump(FDCP)with perfect current matching and low output current noise is realized for phase-locked loops(PLLs).An easily stable common-mode feedback(CMFB)circuit which can handle high ...A fully-differential charge pump(FDCP)with perfect current matching and low output current noise is realized for phase-locked loops(PLLs).An easily stable common-mode feedback(CMFB)circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.展开更多
In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented. The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescen...In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented. The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescent current in skip mode for light loads, and produces low ripple in linear mode for heavy loads, which closes the gap between linear mode and skip mode with active regulation; a multi-mode charge pump employing the technique has been implemented in the UMC 0.6-μm-BCD process. The results indicate that the charge pump works well and effectively; it has low ripple with special regulation, and minimizes the size of the capacitance, then decreases the area of the PCB board. The adjustable output of the positive charge pump is 10-30 V, and the maximum output ripple is 100 mV when the load current is 200 mA. The line regulation is 0.2%/V, and load regulation is 0.075%.展开更多
To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconduct...To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.展开更多
A low ripple switched capacitor charge pump applicable to phase change memory (PCM) is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio betw...A low ripple switched capacitor charge pump applicable to phase change memory (PCM) is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase (Vo is the prospective output voltage). In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.展开更多
This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doubl...This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm^2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.展开更多
A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-lik...A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-like charge pump. An optimal frequency is a compromise between the rise time and the dynamic power dissipation. The optimization of the two-phase nonoverlapping clock generator circuit improves the efficiency. Simulation results based on 1.2 μm complementary metal-oxide-semiconductor (CMOS) technology parameters verify the efficiency of the design.展开更多
This paper presents a new circuit scheme to control the current surge in the boosting phase of an radio frequency identification-nonvolative memory pump.By introducing a circuit block consisting of a current reference...This paper presents a new circuit scheme to control the current surge in the boosting phase of an radio frequency identification-nonvolative memory pump.By introducing a circuit block consisting of a current reference and a current mirror,the new circuit scheme can keep the period-average current of the pump constantly below the desired level,for example,2.5μA.Therefore,it can prevent the rectified supply of the RFID tag IC from collapsing in the boosting phase of the pump.The presented scheme could effectively reduce the voltage drop on the rectified supply from more than 50%to even zero,but could cost less area.Moreover,an analytical expression to calculate the boosting time of a pump in the new scheme is developed.展开更多
An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed c...An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC-DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump's power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.展开更多
An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 μm CMOS process technology. The filter system with...An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point (ⅡP3) is 16.621 dBm, with 50Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS (global positioning system) and Bluetooth systems.展开更多
A diagram representation method is proposed to interpret the complicated charge pumping(CP) processes. The fast and slow traps in CP measurement are defined.Some phenomena such as CP pulse rise/fall time dependence,...A diagram representation method is proposed to interpret the complicated charge pumping(CP) processes. The fast and slow traps in CP measurement are defined.Some phenomena such as CP pulse rise/fall time dependence, frequency dependence,the voltage dependence for the fast and slow traps,and the geometric CP component are clearly illustrated at a glance by the diagram representation.For the slow trap CP measurement,there is a transition stage and a steady stage due to the asymmetry of the electron and hole capture,and the CP current is determined by the lower capturing electron or hole component.The method is used to discuss the legitimacy of the newly developed modified charge pumping method.展开更多
A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output...A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62274189the Natural Science Foundation of Guangdong Province,China,under Grant 2022A1515011054the Key Area R&D Program of Guangdong Province under Grant 2022B0701180001.
文摘In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.
文摘A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor (CMOS) mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11704190,11874221,and 11504240)the Natural Science Foundation of Jiangsu Province,China(Grant No.BK20171030)
文摘We numerically investigate the valley-polarized current in symmetric and asymmetric zigzag graphene nanoribbons(ZGNRs) by the adiabatic pump, and the effect of spatial symmetry is considered by introducing different pumping regions. It is found that pumping potentials with the symmetry Vp(x,y) = Vp(-x,y)can generate the largest valleypolarized current. The valley-polarized currents I13~L with the pumping potential symmetry Vp(x,y) =Vp(x,-y,) and I14~L with Vp(x,y) = Vp(-x,-y) of symmetric ZGNRs are much smaller than those of asymmetric ZGNRs. We also find I13~L and I14~L of symmetric ZGNRs decrease and increase with the increasing pumping amplitude, respectively. Moreover, the dephasing effect from the electron-phonon coupling within the Buttiker dephasing scheme is introduced. The valley-polarized current of the symmetric ZGNRs with Vp(x,y)= Vp(x,-y) increases with the increase of the dephasing strength while that with Vp(x,y) = Vp(-x,-y) decreases as the dephasing strength increases.
基金Supported by the National High Technology Re-search and Development Programof China (2004AA122310)
文摘A self-balanced charge pump (CP) with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor (CMOS) process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector (PFD) was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11274059,11574045,and 11704165)
文摘We report a theoretical study of pumped spin currents in a silicene-based pump device, where two time-dependent staggered potentials are introduced through the perpendicular electric fields and a magnetic insulator is considered in between the two pumping potentials to magnetize the Dirac electrons. It is shown that giant spin currents can be generated in the pump device because the pumping can be optimal for each transport mode, the pumping current is quantized. By controlling the relevant parameters of the device, both pure spin currents and fully spin-polarized currents can be obtained.Our results may shed a new light on the generation of pumped spin currents in Dirac-electron systems.
基金Supported by the National Key Pre-Research Project of China (413010701-3)
文摘A 3.5 times PLL clock frequency multiplier for low voltage different signal (LVDS) driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator (VCO) is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .
基金supported in party by the National Key Technological Program of China under Grant No.2008ZX01035-001supported by National Natural Science Foundation of China under Grant No.60870001
文摘In wireless sensor network (WSN), the communication node is the heart of the whole system. Negative bias temperature instability (NBTI) is becoming one of the most important factors that decide the life time of node chips, especially with the feature size declining. In this paper, the NBTI impact on the front-end circuits in the WSN nodes is studied, such as voltage-controlled oscillator (VCO), charge pump (CP), low noise amplifier (LNA), and even the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. It is shown that the phase noise of the VCO will be deteriorated, the current mismatch of the CP and the noise figure of the LNA will both be increased, and the sensitivity and the adjacent channel selectivity (ACS) will be depressed by NBTI. The conclusions are proved by simulation results using HJTC 0.18 μm technology.
基金supported by the Chinese National High-Tech Research and Development Program(No.2006AA04A108)the National Natural Science Foundation of China(No.2008AA010703).
文摘A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z282)the National Natural Science Foundation of China(No.60876019)
文摘A fully-differential charge pump(FDCP)with perfect current matching and low output current noise is realized for phase-locked loops(PLLs).An easily stable common-mode feedback(CMFB)circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.
基金supported by the National Natural Science Foundation of China(No.60876023)
文摘In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented. The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescent current in skip mode for light loads, and produces low ripple in linear mode for heavy loads, which closes the gap between linear mode and skip mode with active regulation; a multi-mode charge pump employing the technique has been implemented in the UMC 0.6-μm-BCD process. The results indicate that the charge pump works well and effectively; it has low ripple with special regulation, and minimizes the size of the capacitance, then decreases the area of the PCB board. The adjustable output of the positive charge pump is 10-30 V, and the maximum output ripple is 100 mV when the load current is 200 mA. The line regulation is 0.2%/V, and load regulation is 0.075%.
基金supported by the National Natural Science Foundation of China(No.60876023)
文摘To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.
基金supported by the National Key Basic Research Program of China(Nos.2010CB934300,2011CBA00607,2011CB932800)the National Integrated Circuit Research Program of China(No.2009ZX02023-003)+1 种基金the National Natural Science Foundation of China(Nos. 60906004,60906003,61006087,61076121)the Science and Technology Council of Shanghai(No.1052nm07000)
文摘A low ripple switched capacitor charge pump applicable to phase change memory (PCM) is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase (Vo is the prospective output voltage). In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.
文摘This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm^2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.
文摘A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-like charge pump. An optimal frequency is a compromise between the rise time and the dynamic power dissipation. The optimization of the two-phase nonoverlapping clock generator circuit improves the efficiency. Simulation results based on 1.2 μm complementary metal-oxide-semiconductor (CMOS) technology parameters verify the efficiency of the design.
文摘This paper presents a new circuit scheme to control the current surge in the boosting phase of an radio frequency identification-nonvolative memory pump.By introducing a circuit block consisting of a current reference and a current mirror,the new circuit scheme can keep the period-average current of the pump constantly below the desired level,for example,2.5μA.Therefore,it can prevent the rectified supply of the RFID tag IC from collapsing in the boosting phase of the pump.The presented scheme could effectively reduce the voltage drop on the rectified supply from more than 50%to even zero,but could cost less area.Moreover,an analytical expression to calculate the boosting time of a pump in the new scheme is developed.
基金Project supported by the National High Technology Research and Development Program of China (No.2005AA1Z1193)
文摘An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC-DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump's power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.
文摘An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point (ⅡP3) is 16.621 dBm, with 50Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS (global positioning system) and Bluetooth systems.
基金Project supported by the Micro/Nano-Electronics Science and Technology Innovation Platform of Fudan University,National Natural Science Foundation of China(No.60936005)the National VLSI Project(No.2009ZX02035-003).
文摘A diagram representation method is proposed to interpret the complicated charge pumping(CP) processes. The fast and slow traps in CP measurement are defined.Some phenomena such as CP pulse rise/fall time dependence, frequency dependence,the voltage dependence for the fast and slow traps,and the geometric CP component are clearly illustrated at a glance by the diagram representation.For the slow trap CP measurement,there is a transition stage and a steady stage due to the asymmetry of the electron and hole capture,and the CP current is determined by the lower capturing electron or hole component.The method is used to discuss the legitimacy of the newly developed modified charge pumping method.
基金Project supported by the National Defense Pre-Research Project of China(No.51308010610)
文摘A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.