Refined control of etched profile in microelectronic devices during plasma etching process is one of the most important tasks of front-end and back-end microelectronic devices manufacturing technologies. A comprehensi...Refined control of etched profile in microelectronic devices during plasma etching process is one of the most important tasks of front-end and back-end microelectronic devices manufacturing technologies. A comprehensive simulation of etching profile evolution requires knowledge of the etching rates at all the points of the profile surface during the etching process. Electrons do not contribute directly to the material removal, but they are the source, together with positive ions, of the profile charging that has many negative consequences on the final outcome of the process especially in the case of insulating material etching. The ability to simulate feature charging was added to the 3D level set profile evolution simulator described earlier. The ion and electron fluxes were computed along the feature using Monte Carlo method. The surface potential profiles and electric field for the entire feature were generated by solving Laplace equation using finite elements method. Calculations were performed in the case of simplified model of Ar+/CF4 non-equilibrium plasma etching of SiO2.展开更多
In advanced technologies, single event upset reversal(SEUR) due to charge sharing can make the upset state of SRAM cells recover to their initial state, which can reduce the soft error for SRAMs in radiation environme...In advanced technologies, single event upset reversal(SEUR) due to charge sharing can make the upset state of SRAM cells recover to their initial state, which can reduce the soft error for SRAMs in radiation environments. By using the full 3D TCAD simulations, this paper presents a new kind of SEUR triggered by the charge collection of the Off-PMOS and the delayed charge collection of the On-NMOS in commercial 40-nm 6 T SRAM cells. The simulation results show that the proposed SEUR can not occur at normal incidence,but can present easily at angular incidence. It is also found that the width of SET induced by this SEUR remains the same after linear energy transfer(LET) increases to a certain value. In addition, through analyzing the effect of the spacing, the adjacent transistors, the drain area, and some other dependent parameters on this new kind of SEUR, some methods are proposed to strengthen the recovery ability of SRAM cells.展开更多
As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing...As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.展开更多
A finite-volume charge method has been proposed to simulate PIN diodes and insulated-gate bipolar transistor(IGBT)devices using SPICE simulators by extending the lumped-charge method.The new method assumes local quasi...A finite-volume charge method has been proposed to simulate PIN diodes and insulated-gate bipolar transistor(IGBT)devices using SPICE simulators by extending the lumped-charge method.The new method assumes local quasi-neutrality in the undepleted N^(-)base region and uses the total collector current,the nodal hole density and voltage as the basic quantities.In SPICE implementation,it makes clear and accurate definitions of three kinds of nodes—the carrier density nodes,the voltage nodes and the current generator nodes—in the undepleted N^(-)base region.It uses central finite difference to approximate electron and hole current generators and sets up the current continuity equation in a control volume for every carrier density node in the undepleted N^(-)base region.It is easy to increase the number of nodes to describe the fast spatially varying carrier density in transient processes.We use this method to simulate IGBT devices in SPICE simulators and get a good agreement with technology computer-aided design simulations.展开更多
基金The Ministry of Education and Science, Republic of Serbai, Projects O171037 and III41011
文摘Refined control of etched profile in microelectronic devices during plasma etching process is one of the most important tasks of front-end and back-end microelectronic devices manufacturing technologies. A comprehensive simulation of etching profile evolution requires knowledge of the etching rates at all the points of the profile surface during the etching process. Electrons do not contribute directly to the material removal, but they are the source, together with positive ions, of the profile charging that has many negative consequences on the final outcome of the process especially in the case of insulating material etching. The ability to simulate feature charging was added to the 3D level set profile evolution simulator described earlier. The ion and electron fluxes were computed along the feature using Monte Carlo method. The surface potential profiles and electric field for the entire feature were generated by solving Laplace equation using finite elements method. Calculations were performed in the case of simplified model of Ar+/CF4 non-equilibrium plasma etching of SiO2.
基金Supported by National Natural Science Foundation of China(Nos.61176030 and 61373032)Specialized Research Fund for the Doctor Program of Higher Education of China(No.20124307110016)
文摘In advanced technologies, single event upset reversal(SEUR) due to charge sharing can make the upset state of SRAM cells recover to their initial state, which can reduce the soft error for SRAMs in radiation environments. By using the full 3D TCAD simulations, this paper presents a new kind of SEUR triggered by the charge collection of the Off-PMOS and the delayed charge collection of the On-NMOS in commercial 40-nm 6 T SRAM cells. The simulation results show that the proposed SEUR can not occur at normal incidence,but can present easily at angular incidence. It is also found that the width of SET induced by this SEUR remains the same after linear energy transfer(LET) increases to a certain value. In addition, through analyzing the effect of the spacing, the adjacent transistors, the drain area, and some other dependent parameters on this new kind of SEUR, some methods are proposed to strengthen the recovery ability of SRAM cells.
基金Project supported by the Key Program of the National Natural Science Foundation of China (Grant No. 61133007)the National Natural Science Foundation of China (Grant Nos. 61006070 and 61076025)
文摘As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.
文摘A finite-volume charge method has been proposed to simulate PIN diodes and insulated-gate bipolar transistor(IGBT)devices using SPICE simulators by extending the lumped-charge method.The new method assumes local quasi-neutrality in the undepleted N^(-)base region and uses the total collector current,the nodal hole density and voltage as the basic quantities.In SPICE implementation,it makes clear and accurate definitions of three kinds of nodes—the carrier density nodes,the voltage nodes and the current generator nodes—in the undepleted N^(-)base region.It uses central finite difference to approximate electron and hole current generators and sets up the current continuity equation in a control volume for every carrier density node in the undepleted N^(-)base region.It is easy to increase the number of nodes to describe the fast spatially varying carrier density in transient processes.We use this method to simulate IGBT devices in SPICE simulators and get a good agreement with technology computer-aided design simulations.
