Flip Chip技术在集成电路封装中的应用

阐述从集成电路封装发展现状、Flip Chip技术内涵、Flip Chip技术在集成电路封装中的应用剖析、市场发展展望等多个角度,探讨在集成电路封装中,应用Flip Chip技术的必要性和重要性。

EVOLUTION OF MICROSTRUCTURE OF Sn-Ag-Cu LEAD-FREE FLIP CHIP SOLDER JOINTS DURING AGING PROCESS

Flip chip bonding has become a primary technology that has found application in the chip interconnection process in the electronic manufacturing industry in recent years. The solder joints of the flip chip bonding are small and consist of complicated microstructures such as Sn solution, eutectic mixture, and intermetallic compounds （IMCs）, whose mechanical performance is quite different from the original solder bulk. The evolution of microstructure of the flip chip solder joints under thermal aging was analyzed. The results show that with an increase in aging time, coarsening of solder bulk matrix and AuSn4 IMCs occurred within the solder. The IMCs that are formed at the bottom side of the flip chip bond were different from those on the top side during the aging process. （Cu, Ni, Au）0Sn5 were formed at the interfaces of both sides, and large complicated （Au,Ni, Cu）Sn4 IMCs appeared for some time near the bottom interface after aging, but they disappeared again and thus （Cu,Ni, Au ）0Sn5 IMC thickness increased considerably. The influence of reflow times during the flip chip bonding （as-bonded condition） on the characteristics of interfacial IMCs was weakened when subjected to the aging process.

Effects of ultrasonic bonding parameters on reliability of flip chip GaN-based light emitting diode

This work applied the ultrasonic bonding to package flip chip GaN-based light emitting diodes （flip chip LEDs） on Si substrates. The effects of ultrasonic bonding parameters on the reliability of flip chip GaN-based LED were investigated. In the sequent aging tests, samples were driven with a constant current of 80 mA for hundreds hours at the room temperature. It was found that the electroluminescence （EL） intensity variation had a large correlation to the ultrasonic power, and then to the bonding temperature and force. A high bonding temperature and ultrasonic power and a proper bonding force improved the EL intensity significantly. It was contributed to a strong atom inter-diffusion forming a stable joint at the bonding interface, The temperature fluctuation in the aging test was the main factor to generate a high inner stress forming delamination at the interface between the chip and Au bump. As a result, delamination had retarded the photons to emit out of the LED packaging and decay its EL intensity.

Ultrasonic power features of wire bonding and thermosonic flip chip bonding in microelectronics packaging

The driving voltage and current signals of piezoceramic transducer (PZT) were measured directly by designing circuits from ultrasonic generator and using a data acquisition software system. The input impedance and power of PZT were investigated by using root mean square (RMS) calculation. The vibration driven by high frequency was tested by laser Doppler vibrometer (PSV-400-M2). And the thermosonic bonding features were observed by scanning electron microscope (JSM-6360LV). The results show that the input power of bonding is lower than that of no load. The input impedance of bonding is greater than that of no load. Nonlinear phase, plastic flow and expansion period, and strengthening bonding process are shown in the impedance and power curves. The ultrasonic power is in direct proportion to the vibration displacement driven by the power, and greater displacements driven by high power (>5 W) result in welding failure phenomena, such as crack, break, and peeling off in wedge bonding. For thermosonic flip chip bonding, the high power decreases position precision of bonding or results in slippage and rotation phenomena of bumps. To improve reliability and precision of thermosonic bonding, the low ultrasonic power (about 1-5 W) should be chosen.

Flip Chip结构的IC信号完整性仿真分析

针对Flip Chip封装型芯片设计过程中存在的传输线阻抗不连续与串扰过大等问题,从层叠设置与板材介质厚度两个角度提出了一种基于阻抗、串扰的仿真分析设计方法,主要涉及两个方面:对于由信号参考平面被分割而造成的阻抗突变问题,通过添加参考平面而使信号具有完整的回流路径,使得传输线的阻抗在平面分割处由167.5Ω降至52.5Ω;对于因布线密度过大而造成的走线之间的串扰系数偏高的问题,通过减小板材的介质厚度使传输线间串扰系数的最大值从17.26%降至14.01%。仿真结果表明,此设计方法有效降低了芯片设计中潜在的信号完整性风险,提高了芯片的可靠性和稳定性。

The Numerical Analysis of Strain Behavior at Solder Joint and Interface of Flip Chip Package

The flip chip package is a kind of advanced electri ca l packages. Due to the requirement of miniaturization, lower weight, higher dens ity and higher performance in the advanced electric package, it is expected that flip chip package will soon be a mainstream technology. The silicon chip is dir ectly connected to printing circuit substrate by SnPb solder joints. Also, the u nderfill, a composite of polymer and silica particles, is filled in the gap betw een the chip and substrate around the solder joints to improve the reliabili ty of solder joints. When flip chip package specimen is tested with thermal cycl ing, the cyclic stress/strain response that exists at the underfill interfaces and solder joints may result in interfacial crack initiation and propagation. Therefore, the chip cracking and the interfacial delamination between underfill and chip corner have been investigated in many studies. Also, most researches h ave focused on the effect of fatigue and creep properties of solder joint induce d by the plastic strain alternation and accumulation. The nuderfill must have lo w viscosity in the liquid state and good adhesion to the interface after solidif ying. Also, the mechanical behavior of such epoxy material has much dependen ce on temperature in its glass transition temperature range that is usually cove red by the temperature range of thermal cycling test. Therefore, the materia l behavior of underfill exists a significant non-linearity and the assumption o f linear elastic can lack for accuracy in numerical analysis. Through numerical analysis, this study had some comparisons about the effect of linear and non -linear properties of underfill on strain behaviors around the interface of fli p chip assembly. Especially, the deformation tendency inside solder bumps could be predicted. Also, it is worthily mentioned that we have pointed out which comp onent of plastic strain, thus, either normal or shear, has dominant influence to the fatigue and creep of solder bump, which have not brought up before. About the numerical analysis to the thermal plastic strain occurs in flip chip i nterconnection during thermal cycling test, a commercial finite element software , namely, ANSYS, was employed to simulate the thermal cycling test obeyed by MIL-STD-883C. The temperatures of thermal cycling ranged from -55 ℃ to 125 ℃ with ramp rate of 36 ℃/min and a dwell time of 25 min at peak temperature. T he schematic drawing of diagonal cross-section of flip chip package composed of FR-4 substrate, silicon chip, underfill and solder bump was shown as Fig.1. Th e numerical model was two-dimensional (2-D) with plane strain assumption and o nly one half of the cross-section was modeled due to geometry symmetry. The dim ensions and boundary conditions of numerical model were shown in Fig.2. The symm etric boundary conditions were applied along the left edge of the model, and the left bottom corner was additional constrained in vertical direction to prevent body motion. The finite element meshes of overall and local numerical model was shown as Fig.3. In this study, two cases of material model were used to describe the material behavior of the underfill: the case1 was linear elastic model that assumed Young’s Modulus (E) and thermal expansion coefficient (CTE) were consta nt during thermal cycling; the case2 was MKIN model (in ANSYS) that had nonlinea r temperature-dependent stress-strain relationship and temperature-dependent CTE. The material model applied to the solder bump was ANAND model (in ANSYS) th at described time-dependent plasticity phenomenon of viscoplastic material. Bot h the FR-4 substrate and silicon chip were assumed as temperature-independent elastic material; moreover, FR-4 substrate is orthotropic while silicon chip is isotropic. From the comparison between numerical results of linear and nonlinear material a ssumption of underfill, (i.e. case1 and case2), the quantities of plastic strain around the interconnection from case1 are higher than that in case2. Thus, the linear

Flip Chip Die-to-Wafer Bonding Review:Gaps to High Volume Manufacturing

Flip chip die-to-wafer bonding faces challenges for industry adoption due to a variety of technical gaps or process integration factors that are not fully developed to high volume manufacturing(HVM)maturity.In this paper,flip-chip and wire bonding are compared,then flip-chip bonding techniques are compared to examine advantages for scaling and speed.Specific recent 3-year trends in flip-chip die-to-wafer bonding are reviewed to address the key gaps and challenges to HVM adoption.Finally,some thoughts on the care needed by the packaging technology for successful HVM introduction are reviewed.

Sampling Moiré method for full-field deformation measurement: A brief review

The sampling Moiré(SM) method is one of the vision-based non-contact deformation measurement methods, which is a powerful tool for structural health monitoring and elucidation of damage mechanisms of materials. In this review, the basic principle of the SM method for measuring the twodimensional displacement and strain distributions is introduced. When the grid is not a standard orthogonal grating and cracks exist on the specimen surface, the measurement methods are also stated. Two of the most typical application examples are described in detail. One is the dynamic deflection measurement of a large-scale concrete bridge, and the other is the residual thermal strain measurement of small-scale flip chip packages. Several further development points of this method are pointed out. The SM method is expected to be used for deformation measurement of various structures and materials for residual stress evaluation, crack location prediction, and crack growth evaluation on broad scales.

Progress in research of GaN-based LEDs fabricated on SiC substrate

The influence of buffer layer growth conditions on the crystal quality and residual stress of GaN film grown on silicon carbide substrate is investigated. It is found that the A1GaN nucleation layer with high growth temperature can efficiently decrease the dislocation density and stress of the GaN film compared with A1N buffer layer. To increase the light extraction efficiency of GaN-based LEDs on SiC substrate, flip-chip structure and thin film flip-chip structure were designed and optimized. The fabricated blue LED had a maximum wall-plug efficiency of 72% at 80 mA. At 350 mA, the output power, the Vf, the dominant wavelength, and the wall-plug efficiency of the blue LED were 644 roW, 2.95 V, 460 nm, and 63%, respectively.

A novel approach for flip chip inspection based on improved SDELM and vibration signals

This paper proposes a novel nondestructive diagnostic method for flip chips based on an improved semi-supervised deep extreme learning machine(ISDELM)and vibration signals.First,an ultrasonic transducer is used to generate and focus ultrasounds on the surface of the flip chip to excite it,and a laser scanning vibrometer is applied to acquire the chip’s vibration signals.Then,an extreme learning machine-autoencoder(ELM-AE)structure is adopted to extract features from the original vibration signals layer by layer.Finally,the study proposes integrating the ELM with sparsity neighboring reconstruction to diagnose defects based on unlabeled and labeled data.The ISDELM algorithm is applied to experimental vibration data of flip chips and compared with several other algorithms,such as semi-supervised ELM(SS-ELM),deep ELM,stacked autoencoder,convolutional neural network,and ordinary SDELM.The results show that the proposed method is superior to the several currently available algorithms in terms of accuracy and stability.

Light-extraction enhancement of freestanding GaN-based flip-chip light-emitting diodes using two-step roughening methods

The light extraction enhancement of freestanding GaN-based flip-chip light-emitting diodes （FS- FCLEDs） using two-step roughening methods is investigated. The output power of LEDs fabricated by using one-step and two-step roughening methods are compared. The results indicate that two-step roughening meth- ods show more potential for light extraction. Compared with flat FS-FCLEDs, the output power of FS-FCLEDs with a nanotextured hemisphere surface shows an enhancement of 90.7%.

Preparation of GaN-on-Si based thin-film flip-chip LEDs

GaN based MQW epitaxial layers were grown on Si （111） substrate by MOCVD using AIN as the buffer layer. High light extraction LEDs were prepared by substrate transferring technology in combination with thin-film and flip-chip design. The blue and white 1.1 × 1.1 mm2 LED lamps are measured. The optical powers and external quantum efficiency for silicone encapsulated blue lamp are 546 mW, and 50.3% at forward current of 350 mA, while the photometric light output for a white lamp packaged with standard YAG phosphor is 120.1 lm.

Preparation and atmospheric wet-reflow of indium microbump for low-temperature flip-chip applications

An urgent demand for lowering bonding temperature has been put forward by advanced flip-chip integration such as micro-LED packaging and heterogeneous integration of semiconductor devices.Indium microbump with low-melting point has attracted attention for its potential use as the interconnection intermediate,and the development of its fabrication process is therefore of great attraction.To reveal the critical process factors for successfully fabricating a high-density In microbump array,this paper investigated a simple process flow of In patterning and reflow and detailed the flux-assisted wet reflow process.Critical process conditions,including the patterned In volume,alignment accuracy,reflow reagent liquidity,and temperature profile,were described,with a particular emphasis on the role of surface tension of molten indium film during the formation of spherical microbumps.A high-density indium ball array with an overall yield greater than 99.7%can be obtained,which suggests that the In patterning and wet-reflow processes are robust and that a high-quality microbump array could be readily formed with low equipment requirements.Furthermore,the interfacial reaction characteristics between In microbump and Au adhesion layer were investigated under thermal aging conditions,which revealed lateral intermetallic growth of AuIn2 compound and well-retained interfacial strength even after prolonged aging.

Flexible electronics manufacturing technology and equipment

Flexible electronics such as mechanically compliant displays,sensors and solar cells,have important applications in the fields of energy,national defence and biomedicine,etc.Various types of flexible electronics have been proposed or developed by the improvements in structural designs,material properties and device integrations.However,the manufacturing of flexible electronics receives little attention,which limits its mass production and industrialization.The increasing demands on the size,functionality,resolution ratio and reliability of flexible electronics bring several significant challenges in their manufacturing processes.This work aims to report the state-of-art technologies and applications of flexible electronics manufacturing.Three key technologies including electrohydrodynamic direct-writing,flip chip and automatic optical inspection are highlighted.The mechanism and developments of these technologies are discussed in detail.Based on these technologies,the present work develops three kinds of manufacturing equipment,i.e.,inkjet printing manufacturing equipment,robotized additive manufacturing equipment,and roll-to-roll manufacturing equipment.The advanced manufacturing processes,equipment and systems for flexible electronics pave the way for applications of new displays,smart sensing skins and epidermal electronics,etc.By reviewing the developments of flexible electronics manufacturing technology and equipment,it can be found that the existing advances greatly promote the applications and commercialization of flexible electronics.Since flexible electronics manufacturing contains many multi-disciplinary problems,the current investigations are confronted with great challenges.Therefore,further developments of the reviewed manufacturing technology and equipment are necessary to break the current limitations of manufacturing resolution,efficiency and reliability.

Optical and electrical properties of a spiral LED filament

This paper introduces a new type of spiral white light-emitting diodes（WLED） filament with high luminous efficiency and uniform optical performance. The optical and thermal properties of the flexible filament were investigated at different stretching heights, namely 0, 1, 2, and 3 cm. The results indicated that the filament showed the best optical characteristics at the stretching height of 2 cm, because of good heat dissipation. In addition, the radiation temperature of the filament was inversely proportional to the output luminous flux. The reliability of the filament at a stretching height of 2 cm was also evaluated after 1000 h of use. The result demonstrated that the luminous flux decay of the bulb was only 0.85%. The flexible spiral WLED filament exhibiting high luminous flux and good reliability could be adapted to promote industrial development in the near future.

Effect of optical illumination on DDR IMPATT diode at 36 GHz

A reverse biased p-n junction diode with proper resonant cavity and boundary conditions is able to generate rf power and shows normal DC and small signal properties designed with semiconductor materials like 4H-SiC, GaAs, InP, Si-based DDR IMPATT structure at Ka band with dark condition. But when it is exposed to optical illumination through a proper optical window for both top mounted（TM） and flip chip（FC） configuration,it shows the influence on the oscillator performances in that band of frequency. The simulated results are analyzed for 36 GHz window frequency in each of the diodes and relative differences are found in power output and frequency of all these diodes with variable intensities of illumination. Finally it is found that optical control has immense effect in both FC and TM mode regarding the reduction of output power and shifting of operating frequency from which optimization is done for the best optically sensitive material for IMPATT diode.