Ant colony optimization approach for test scheduling of system on chip

It is necessary to perform the test of system on chip,the test scheduling determines the test start and finishing time of every core in the system on chip such that the overall test time is minimized.A new test scheduling approach based on chaotic ant colony algorithm is presented in this paper.The optimization model of test scheduling was studied,the model uses the information such as the scale of test sets of both cores and user defined logic.An approach based on chaotic ant colony algorithm was proposed to solve the optimization model of test scheduling.The test of signal integrity faults such as crosstalk were also investigated when performing the test scheduling.Experimental results on many circuits show that the proposed approach can be used to solve test scheduling problems.

Random testing for system-level functional verification of system-on-chip

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.

The embedded design verification test of microwave circuit modules based on specific chips

In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of microwave circuit modules and approach of hardware design and software design,and finally verifies the embedded design of microwave circuit modules based on specific chips.

Design and Test of Multibus Adapter System on a Chip for Fault Tolerant Computer Systems

In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..

Scheduling method based on virtual flattened architecture for Hierarchical system-on-chip

As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively.

on-Chip SRAM内建自测试及其算法的研究

具体研究on-Chip SRAM的内建自测试及其算法。在引入嵌入式存储器内建自测试的基础上,详细分析on-Chip SRAM内建自测试的具体实现方法,反映出内建自测试对于简化测试程序和缩短测试时间,从而降低测试成本的重要性。详细描述在测试on-Chip SRAM时常用的算法,并具体分析非传统性测试算法——Hammer算法和Retention算法。

基于TestStand的音频芯片自动测量系统

为了解决利用仪器手动测量音频芯片性能效率不高,易出错的问题,根据音频芯片测试系统的原理,以LabVIEW、TestStand为平台进行系统化,模块化自动测量。本文介绍了该系统的硬件、软件构成,详细介绍软件设计及功能实现流程。运行结果表明:该系统运行稳定,精度高。

液相芯片多重检测技术在临床检验应用的研究进展

液相芯片多重检测技术是一种利用混悬在液相中的分类编码微球作为反应及信号检测载体的多重检测技术,它充分利用发展成熟的流式细胞术检测原理,能对临床大多数生物分子(如核酸、蛋白质等)进行高通量分析。该技术目前已在医学检验应用研究中广泛使用。本文着重归纳了液相芯片多重检测技术在呼吸系统、消化系统、生殖系统、神经系统、内分泌系统、泌尿系统、运动系统等各大系统疾病与核酸、蛋白质检测方面的临床检验应用研究,发现其性能高,有可观的应用前景。此外,将液相芯片多重检测技术与ELISA法、PCR法等传统方法进行比较后,发现液相芯片多重检测技术具有线性范围好、高通量、检测速度快、灵敏度高、特异性强、准确性高等优点,表明该技术更适用于临床疾病指标的筛查。

CORE-UNIFIED SOC TEST DATA COMPRESSION AND APPLICATION

The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.

Study on MCM Interconnect Test Generation Based on Ant Algorithm with Mutation Operator

A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.

通井规携屑性能研究结构及参数优化

针对一体化井筒准备作业中岩屑通过通井规效果差,导致通井规携屑能力低的问题,以携屑能力为性能指标,采用正交试验法对通井规进行结构优化设计,得到了最优结构参数:过流道深度6 mm、过流道螺旋角度80°、过流道宽度40 mm、扶正套锥角11°;同时以最优结构参数对通井规作业参数进行优选,优选出最佳作业参数:循环排量1.1 m^(3)/min、转速60 r/min。研究结果表明,对通井规结构参数优化和作业参数优选,提高了通井规携屑能力,为通井规结构参数和工况参数的优化研究提供了参考,具有指导和借鉴意义。

半刀宽插铣冲击力有限元分析与实验研究

半刀宽插铣是一种常见的型腔加工方式,在顺铣切入和逆铣切出时由于刀—屑接触宽度突变会产生较大冲击,严重影响刀具使用寿命。通过有限元计算与实验相结合的方式,对半刀宽逆铣加工中的冲击力学行为进行研究。以40Cr合金钢为研究对象,建立半刀宽逆铣有限元计算模型,根据加工中刀—屑接触宽度与切削力的变化特点,以刀—屑接触宽度发生突变对应时刻的切向力表征冲击力,采用极差分析法与单因素分析法研究各切削参数对刀具冲击力的影响规律,并通过实验验证了模型的有效性。实验结果表明,仿真与实验冲击力的相对误差在10%以内,证明该有限元模型可用于半刀宽插铣冲击力预测和切削参数优化;冲击力与插铣步距和每齿进给量成正比,随着切削速度的增加,冲击力先增加后减小。

Area-time associated test cost model for SoC and lower bound of test time

A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.

GaN收发多功能芯片在片集成测试优化

为了解决传统开关集成测试方案中严苛的时序同步要求,根据GaN收发多功能芯片的在片电参数测试需求,采用环行器优化测试方案,减少芯片测试时序变量,提高了芯片测试程序的鲁棒性,并且利用去嵌入技术对系统的校准进行简化。通过典型器件的测试对方案进行了验证,结果表明,环行器优化测试方案与传统的开关集成测试方案输出结果基本一致,优化测试方案是有效的。

Point-of-Care Testing Using Three Dimensional Optical Biosensor Based on Microfluidic Technology

We have presented a three dimensional optical protein chip that fulfills the demanding for point-of-care diagnostics in terms of ease-of-use (one step assay), miniaturization (5 μl). The artful combination of magnetic nanoparticles on chip and total internal reflection imaging (TIRI) technology permits the sensitive and rapid detection of hs-CRP (high-sensitivity C-reactive protein). The whole test was complete within 10 min using “all in one step” assay with a limit of detection of 0.1 ng/mL hs-CRP. The measuring range for hs-CRP could be extended to 10 ng/mL. The chip can also be used to detect more parameters in blood samples.

基于模糊自适应PID的汽车硅油风扇离合器性能测试系统研究

以汽车硅油风扇离合器为研究对象,结合单片机和传感器技术,开发出性能测试系统.提出模糊自适应PID动态控制算法,设计控制器控制温度,利用速度传感器检测风扇转速,对测试系统进行整体设计,给出了硬件总体设计框图,设计模拟量输入输出电路,并设计对应的软件系统.实验结果表明:测试系统升降温速率最高不超过8.5℃/min,耦合区加温速率约为2.3℃/min,分离区降温速率约为6.6℃/min,系统性能稳定,符合标准.

DFT Techniques in DSP Chip Core NDSP25

Design for Testability(DFT) is critical in chip design.DFT techniques insert hardware logic to an original design,in order to improve testability of the chip,and thus reduce test cost significantly.In this paper,we introduces the most frequently used DFT techniques,then put emphasis on the DFT policy and the DFT realization of the NDSP25 chip core,and analyses the result at last.

面向自主芯片频率扫描实速测试的扫描链分析

随着芯片工艺的不断升级,芯片设计的频率不断提高,时延故障是引起高速芯片失效的重要因素。在硅后验证阶段,由于缺乏一种对芯片全局路径延时测量的手段,传统构建延时测量电路的方式仅能得到特定关键路径的延时变化情况,在芯片失效时无法进行全面的路径延时分析。本文提出一种基于扫描链的频率扫描实速测试方法对芯片内部大量时序路径的延时进行测量并获取时序裕量。针对生成测试向量时间长,依赖专业测试设备的问题,在自研硬件平台上通过自生成多频率测试向量以及改进数据校验算法成功实现了频率扫描实速测试,对芯片测量的路径延时误差在8 ps左右。通过对不同芯片在不同温度下的实验验证了该方法对路径延时表征的有效性,为今后通过延时参数对高速芯片进行环境适应性分析、寿命预测等研究提供了一种快捷有效的方法。

骨骼肌芯片及其在生物医学领域的研究进展

骨骼肌作为人体最丰富的组织之一,是人体运动功能的主要承担者,并且在能量代谢、免疫调节和衰老过程中发挥重要作用。骨骼肌所处的微环境结构复杂,包括多种细胞类型、独特的三维结构以及力学特征。因此,建立高仿生的骨骼肌模型具有一定的挑战性。器官芯片可以精确地模拟人体组织的关键结构和功能特性,从而为骨骼肌模型的建立提供了一种新的途径。本文综述了目前骨骼肌芯片的构建及其在疾病建模、药物评价与再生医学等生物医学研究中的应用。依据人体骨骼肌组织微环境的特点,重点介绍了构建骨骼肌芯片的关键要素,包括动态培养环境、机械刺激、电刺激、血管化与神经化,以及其他工程策略包括各向异性支架的制备与两端锚定的策略等。目前的骨骼肌芯片在细胞来源及功能等方面仍存在一定的局限性。未来通过与基因编辑、生物传感等技术相结合,骨骼肌芯片有望在生物医学研究领域发挥更重要的作用。

基于ZYNQ MPSOC的以太网PHY芯片功能测试方法

随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相应测试方法研究。提出了一种高效的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法。该方法以ZYNQ MPSOC为核心,设计了一种直达应用层面的系统级测试装置,从而减少了与物理层直接交互的行为,有效降低了测试装置及程序开发难度。经试验验证,提出的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法能够用于以太网PHY芯片测试。