This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,o...This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,obtains the results in finite steps and has high efficiency in computation.It can be appliedto the circuits containing multiport nonlinear elements.It is a good method of pre-test analysis for fault cir-cuits in simulation-before-test aproach in analogue circuit diagnosis.展开更多
Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The feature evaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit feature...Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The feature evaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis efficiency. A fault diagnosis illustration validated this method.展开更多
The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studled. Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the ...The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studled. Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the signature dada. The best wavelet function is selected based on the between-category total scatter of signature. The fault dictionary of nonlinear circuits is constructed based on improved back-propagation(BP) neural network. Experimental results demonstrate that the method proposed has high diagnostic sensitivity and fast fault identification and deducibility.展开更多
Analog circuits fault diagnosis is essential for guaranteeing the reliability and maintainability of electronic systems. In this paper, a novel analog circuit fault diagnosis approach is proposed based on greedy kerne...Analog circuits fault diagnosis is essential for guaranteeing the reliability and maintainability of electronic systems. In this paper, a novel analog circuit fault diagnosis approach is proposed based on greedy kernel principal component analysis (KPCA) and one-against-all support vector machine (OAASVM). In order to obtain a successful SVM-based fault classifier, eliminating noise and extracting fault features are very important. Due to the better performance of nonlinear fault features extraction and noise elimination as compared with PCA, KPCA is adopted in the proposed approach. However, when we adopt KPCA to extract fault features of analog circuit, a drawback of KPCA is that the storage required for the kernel matrix grows quadratically, and the computational cost for eigenvector of the kernel matrix grows linearly with the number of training samples. Therefore, GKPCA, which can approximate KPCA with small representation error, is introduced to enhance computational efficiency. Based on the statistical learning theory and the empirical risk minimization principle, SVM has advantages of better classification accuracy and generalization performance. The extracted fault features are then used as the inputs of OAASVM to solve fault diagnosis problem. The effectiveness of the proposed approach is verified by the experimental results.展开更多
At present,ZPW-2000 track circuit fault diagnosis is artificially analyzed and monitored.Its discrimination method not only is low efficient and takes a long period,but also requires highly experienced personnel to an...At present,ZPW-2000 track circuit fault diagnosis is artificially analyzed and monitored.Its discrimination method not only is low efficient and takes a long period,but also requires highly experienced personnel to analyze the data.Therefore,we introduce kernel principal component analysis and stacked auto-encoder network(KPCA-SAD)into the fault diagnosis of ZPW-2000 track circuit.According to the working principle and fault characteristics of track circuit,a fault diagnosis model of KPCA-SAE network is established.The relevant parameters of key components recorded in the data collected by field staff are used as the fault feature parameters.The KPCA method is used to reduce the dimension and noise of fault document matrix to avoid information redundancy.The SAE network is trained by the processed fault data.The model parameters are optimized overall by using back propagation(BP)algorithm.The KPCA-SAE model is simulated in Matlab platform and is finally proved to be effective and feasible.Compared with the traditional method of artificially analyzing fault data and other intelligent algorithms,the KPCA-SAE based classifier has higher fault identification accuracy.展开更多
The most important elements of “intellectual networks” (Smart Grid) are the systems of monitoring the parameters of electrical equipment. Information-measuring systems (IMS), which described in this paper, were prop...The most important elements of “intellectual networks” (Smart Grid) are the systems of monitoring the parameters of electrical equipment. Information-measuring systems (IMS), which described in this paper, were proposed to use together with rapid digital protection against short-circuit regimes in transformer windings. This paper presents an application’s experience of LVI-testing, some results of the use of Frequency Response Analysis (FRA) to check the condition of transformer windings and infra-red control results of electrical equipment. The LVI method and short-circuit inductive reactance measurements are sensitive for detecting such faults as radial, axial winding deformations, a twisting of low-voltage or regulating winding, a losing of winding’s pressing and others.展开更多
Tasks in hard real-time systems are required to meet preset deadlines, even in the presence of transient faults and hence the analysis of worst-case finish time (WCFT) must consider the extra time incurred by re-exe...Tasks in hard real-time systems are required to meet preset deadlines, even in the presence of transient faults and hence the analysis of worst-case finish time (WCFT) must consider the extra time incurred by re-executing tasks that were faulty. Existing solutions can only estimate WCFT and usually result in significant under- or over-estimation. In this work, we conclude that a sufficient and necessary condition of a task set experiencing its WCFT is that its critical task incurs all expected transient faults. A method is presented to identify the critical task and WCFT in O(IVI + IEI) where IVI and IEI are the number of tasks and dependencies between tasks, respectively. This method finds its application in testing the feasibility of directed acyclic graph (DAG) based task sets scheduled in a wide variety of fault-prone multi-processor systems, where the processors could be either homogeneous or heterogeneous, DVS-capable or DVS-incapable, etc. The common practices, which require the same time complexity as the proposed critical-task method, could either underestimate the worst case by up to 25%, or overestimate by 13%. Based on the proposed critical-task method, a simulated-annealing scheduling algorithm is developed to find the energy efficient fault-tolerant schedule for a given DAG task set. Experimental results show that the proposed critical-task method wins over a common practice by up to 40% in terms of energy saving.展开更多
<div style="text-align:justify;"> <span style="font-family:Verdana;">Software systems have become complex and challenging to develop and maintain because of the large size of test cases...<div style="text-align:justify;"> <span style="font-family:Verdana;">Software systems have become complex and challenging to develop and maintain because of the large size of test cases with increased scalability issues. Test case prioritization methods have been successfully utilized in test case management. However, the prohibitively exorbitant cost of large test cases is now the mainstream in the software industry. The growth of agile test-driven development has increased the expectations for software quality. Yet, our knowledge of when to use various path testing criteria for cost-effectiveness is inadequate due to the inherent complexity in software testing. Existing researches attempted to address the issue without effectively tackling the scalability of large test suites to reduce time in regression testing. In order to provide a more accurate way of fault detection in software projects, we introduced novel coverage criteria, called Incremental Cluster-based test case Prioritization (ICP), and investigated its potentials by making a comparative evaluation with three un-clustered traditional coverage-based criteria: Prime-Path Coverage (PPC), Edge-Pair Coverage (EPC) and Edge Coverage (EC) based on mutation analysis. By clustering test suites, based on their dynamic run-time behavior, the number of pair-wise comparisons is reduced significantly. To compare, we analyzed 20 functions from 25 C programs, instrumented faults into the programs, and used the Mull mutation tool to generate mutants and perform a statistical analysis of the results. The experimental results show that ICP can lead to cost-effective improvements in fault detection.</span> </div>展开更多
文摘This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,obtains the results in finite steps and has high efficiency in computation.It can be appliedto the circuits containing multiport nonlinear elements.It is a good method of pre-test analysis for fault cir-cuits in simulation-before-test aproach in analogue circuit diagnosis.
基金the National Natural Science Fundation of China (60372001 90407007)the Ph. D. Programs Foundation of Ministry of Education of China (20030614006).
文摘Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The feature evaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis efficiency. A fault diagnosis illustration validated this method.
基金This project was supported by the National Nature Science Foundation of China(60372001)
文摘The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studled. Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the signature dada. The best wavelet function is selected based on the between-category total scatter of signature. The fault dictionary of nonlinear circuits is constructed based on improved back-propagation(BP) neural network. Experimental results demonstrate that the method proposed has high diagnostic sensitivity and fast fault identification and deducibility.
基金Sponsored by the National Natural Science Foundation of China(Grant No. 61074127)
文摘Analog circuits fault diagnosis is essential for guaranteeing the reliability and maintainability of electronic systems. In this paper, a novel analog circuit fault diagnosis approach is proposed based on greedy kernel principal component analysis (KPCA) and one-against-all support vector machine (OAASVM). In order to obtain a successful SVM-based fault classifier, eliminating noise and extracting fault features are very important. Due to the better performance of nonlinear fault features extraction and noise elimination as compared with PCA, KPCA is adopted in the proposed approach. However, when we adopt KPCA to extract fault features of analog circuit, a drawback of KPCA is that the storage required for the kernel matrix grows quadratically, and the computational cost for eigenvector of the kernel matrix grows linearly with the number of training samples. Therefore, GKPCA, which can approximate KPCA with small representation error, is introduced to enhance computational efficiency. Based on the statistical learning theory and the empirical risk minimization principle, SVM has advantages of better classification accuracy and generalization performance. The extracted fault features are then used as the inputs of OAASVM to solve fault diagnosis problem. The effectiveness of the proposed approach is verified by the experimental results.
基金National Natural Science Foundation of China(No.61763023)。
文摘At present,ZPW-2000 track circuit fault diagnosis is artificially analyzed and monitored.Its discrimination method not only is low efficient and takes a long period,but also requires highly experienced personnel to analyze the data.Therefore,we introduce kernel principal component analysis and stacked auto-encoder network(KPCA-SAD)into the fault diagnosis of ZPW-2000 track circuit.According to the working principle and fault characteristics of track circuit,a fault diagnosis model of KPCA-SAE network is established.The relevant parameters of key components recorded in the data collected by field staff are used as the fault feature parameters.The KPCA method is used to reduce the dimension and noise of fault document matrix to avoid information redundancy.The SAE network is trained by the processed fault data.The model parameters are optimized overall by using back propagation(BP)algorithm.The KPCA-SAE model is simulated in Matlab platform and is finally proved to be effective and feasible.Compared with the traditional method of artificially analyzing fault data and other intelligent algorithms,the KPCA-SAE based classifier has higher fault identification accuracy.
文摘The most important elements of “intellectual networks” (Smart Grid) are the systems of monitoring the parameters of electrical equipment. Information-measuring systems (IMS), which described in this paper, were proposed to use together with rapid digital protection against short-circuit regimes in transformer windings. This paper presents an application’s experience of LVI-testing, some results of the use of Frequency Response Analysis (FRA) to check the condition of transformer windings and infra-red control results of electrical equipment. The LVI method and short-circuit inductive reactance measurements are sensitive for detecting such faults as radial, axial winding deformations, a twisting of low-voltage or regulating winding, a losing of winding’s pressing and others.
基金This work is partially supported by the National High Technology Research and Development 863 Program of China under Grant Nos. 2015AA015304 and 2013AA013202, the National Natural Science Foundation of China under Grant No. 61472052, and Chongqing Research Program under Grant No. cstc2014yykfB40007.
文摘Tasks in hard real-time systems are required to meet preset deadlines, even in the presence of transient faults and hence the analysis of worst-case finish time (WCFT) must consider the extra time incurred by re-executing tasks that were faulty. Existing solutions can only estimate WCFT and usually result in significant under- or over-estimation. In this work, we conclude that a sufficient and necessary condition of a task set experiencing its WCFT is that its critical task incurs all expected transient faults. A method is presented to identify the critical task and WCFT in O(IVI + IEI) where IVI and IEI are the number of tasks and dependencies between tasks, respectively. This method finds its application in testing the feasibility of directed acyclic graph (DAG) based task sets scheduled in a wide variety of fault-prone multi-processor systems, where the processors could be either homogeneous or heterogeneous, DVS-capable or DVS-incapable, etc. The common practices, which require the same time complexity as the proposed critical-task method, could either underestimate the worst case by up to 25%, or overestimate by 13%. Based on the proposed critical-task method, a simulated-annealing scheduling algorithm is developed to find the energy efficient fault-tolerant schedule for a given DAG task set. Experimental results show that the proposed critical-task method wins over a common practice by up to 40% in terms of energy saving.
文摘<div style="text-align:justify;"> <span style="font-family:Verdana;">Software systems have become complex and challenging to develop and maintain because of the large size of test cases with increased scalability issues. Test case prioritization methods have been successfully utilized in test case management. However, the prohibitively exorbitant cost of large test cases is now the mainstream in the software industry. The growth of agile test-driven development has increased the expectations for software quality. Yet, our knowledge of when to use various path testing criteria for cost-effectiveness is inadequate due to the inherent complexity in software testing. Existing researches attempted to address the issue without effectively tackling the scalability of large test suites to reduce time in regression testing. In order to provide a more accurate way of fault detection in software projects, we introduced novel coverage criteria, called Incremental Cluster-based test case Prioritization (ICP), and investigated its potentials by making a comparative evaluation with three un-clustered traditional coverage-based criteria: Prime-Path Coverage (PPC), Edge-Pair Coverage (EPC) and Edge Coverage (EC) based on mutation analysis. By clustering test suites, based on their dynamic run-time behavior, the number of pair-wise comparisons is reduced significantly. To compare, we analyzed 20 functions from 25 C programs, instrumented faults into the programs, and used the Mull mutation tool to generate mutants and perform a statistical analysis of the results. The experimental results show that ICP can lead to cost-effective improvements in fault detection.</span> </div>