A Method on Analog Circuit Fault Diagnosis with Tolerance

In this paper, it is proved that the direction of the node-voltage difference vector, which is the difference between the node-voltage vector at faulty state and the one at the nominal state, is determined only by the location of the faulty clement in linear analog circuits. Considering that the direction of the node-voltage sensitivity vector is the same as the one of the node-voltage difference vector and also considering that the module of the node-voltage sensitivity vector presents the weight of the parameter of faulty element deviation relative to the voltage difference, fault dictionary is set up based on node-voltage sensitivity vectors. A decision algorithm is proposed concerned with both the location and the parameter difference of the faulty element. Single fault and multi-fault can be diagnosed while the circuit parameters deviate within the tolerance range of 10 %.

Particle swarm optimization based RVM classifier for non-linear circuit fault diagnosis

A relevance vector machine (RVM) based fault diagnosis method was presented for non-linear circuits. In order to simplify RVM classifier, parameters selection based on particle swarm optimization (PSO) and preprocessing technique based on the kurtosis and entropy of signals were used. Firstly, sinusoidal inputs with different frequencies were applied to the circuit under test (CUT). Then, the resulting frequency responses were sampled to generate features. The frequency response was sampled to compute its kurtosis and entropy, which can show the information capacity of signal. By analyzing the output signals, the proposed method can detect and identify faulty components in circuits. The results indicate that the fault classes can be classified correctly for at least 99% of the test data in example circuit. And the proposed method can diagnose hard and soft faults.

Combinatorial Optimization Based Analog Circuit Fault Diagnosis with Back Propagation Neural Network

Electronic components' reliability has become the key of the complex system mission execution. Analog circuit is an important part of electronic components. Its fault diagnosis is far more challenging than that of digital circuit. Simulations and applications have shown that the methods based on BP neural network are effective in analog circuit fault diagnosis. Aiming at the tolerance of analog circuit,a combinatorial optimization diagnosis scheme was proposed with back propagation( BP) neural network( BPNN).The main contributions of this scheme included two parts:( 1) the random tolerance samples were added into the nominal training samples to establish new training samples,which were used to train the BP neural network based diagnosis model;( 2) the initial weights of the BP neural network were optimized by genetic algorithm( GA) to avoid local minima,and the BP neural network was tuned with Levenberg-Marquardt algorithm( LMA) in the local solution space to look for the optimum solution or approximate optimal solutions. The experimental results show preliminarily that the scheme substantially improves the whole learning process approximation and generalization ability,and effectively promotes analog circuit fault diagnosis performance based on BPNN.

Research method of circuit fault diagnosis based on FCM

Using fuzzy C cluster mean (FCM), fuzzy theory and neural network, a fault diagnosis method was proposed, which was based on fuzzy C-means clustering algorithm of neural network that was applied in non-linear analog circuits and in diagnoses the ARNIC 429 reception circuit of aviation aircraft avionics. The C cluster algorithm can make the amount of the fuzzy rule automatically and can create an initial fuzzy rule database of fault diagnosis. A type of fuzzy neural network and a fault tree were generated. The algorithm avoids the disadvantage that gets into the part of optimum circumstance. A validate application was implemented, which proves that the method is effective. Therefore, the method is superior to the traditional methods in fault diagnosis, and the efficiency is heavily improved.

Short-circuit fault analysis and isolation strategy for matrix converters

The behavior of matrix converter(MC) drive systems under the condition of MC short-circuit faults is comprehensively investigated. Two isolation strategies using semiconductors and high speed fuses(HSFs) for MC short-circuit faults are examined and their performances are compared. The behavior of MC drive systems during the fuse action time under different operating conditions is explored. The feasibility of fault-tolerant operation during the fuse action time is also studied. The basic selection laws for the HSFs and the requirements for the passive components of the MC drive system from the point view of short-circuit faults are also discussed. Simulation results are used to demonstrate the feasibility of the proposed isolation strategies.

Feature evaluation and extraction based on neural network in analog circuit fault diagnosis

Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The feature evaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis efficiency. A fault diagnosis illustration validated this method.

Improved RBF network application in analog circuit fault isolation

One kind of steepest descent incremental projection learning algorithm for improving the training of radial basis function(RBF)neural network is proposed,which is applied to analog circuit fault isolation.This algorithm simplified the structure of network through optimum output layer coefficient with incremental projection learning(IPL)algorithm,and adjusted the parameters of the neural activation function to control the network scale and improve the network approximation ability.Compared to the traditional algorithm,the improved algorithm has quicker convergence rate and higher isolation precision.Simulation results show that this improved RBF network has much better performance,which can be used in analog circuit fault isolation field.

fault500 kV变电站35 kV串联电抗器故障分析及建议

某500kV变电站主变35kV侧发生一起电容器组串联电抗器短路故障,通过对事故现场检查,结合故障录波器记录,对本次事故发生的过程进行了分析并得出结论。针对本次故障暴露出的问题,从串联电抗器安装位置、在线监测等方面提出了事故防范措施,对于变电站电容器组安全运行具有一定参考价值。

Analysis of the harmful effects to buried oil pipeline from power line short-circuit fault

Based on the transmission line theory of the buried metallic structures, the concerned harmful effects to the buried oil and natural gas pipelines caused by the power line short-circuit fault are further discussed. A closed-form expression of the induced voltage caused by the short-circuit fault of the ultra-high voltage power （UHVAC） transmission line is given. The transmission line model of the buried pipeline is set up and a set of formulas for calculating induced voltage on the pipeline and the parameters of the buried pipeline in actual environment condition are given. At last, the characteristic of the harm^hl effects on the buried pipeline from the power line short-circuit fault are discussed.

A Vague Decision Method for Analog Circuit Fault Diagnosis Based on Description Sphere

This paper proposes a vague decision method for analog circuit fault diagnosis based on description sphere. Firstly, the proposed method uses the wavelet transform as the preprocessor to extract fault features from the output voltages of the circuit un- der test （CUT）. And then, each class sample is trained to produce a minimum description sphere. Finally, the test samples are detected by a defined vague decision rule, which is based on the vague weight distance between the test data and the center of description sphere. The defined decision rule fuses the truth and false membership degrees of the test sample and the weight of the description sphere, and it can effectively deal with the uncertain information. The reliability of the defined decision rule is proved theoretically. This new diagnostic method is first applied to testing two actual circuits, and then it is compared with other two diagnostic methods. The experimental results show that the proposed technique can achieve good performance and reduce the diagnostic time.

Application of thyristor controlled phase shifting transformer excitation impedance switching control to suppress short-circuit fault current level

Short-circuit fault current suppression is a very important issue in modern large-interconnected power networks. Conventional short-circuit current limiters, such as superconducting fault current limiters, have to increase additional equipment investments. Fast power electronics controlled flexible AC transmission system(FACTS)devices have opened a new way for suppressing the fault current levels, while maintaining their normal functionalities for steady-state and transient power system operation and control. Thyristor controlled phase shifting transformer(TCPST) is a beneficial FACTS device in modern power systems, which is capable of regulating regional powerflow. The mathematical model for TCPST under different operation modes is firstly investigated in this study. Intuitively, the phase shifting angle control can adjust the equivalent impedance of TCPST, but the effect has been demonstrated to be weak. Therefore, a novel transformer excitation impedance switching(EIS) control method, is proposed for fault current suppressing, according to the impedance characteristics of TCPST. Simulation results on IEEE 14-bus system have shown considerable current limiting characteristic of the EIS control under various fault types. Also, analysis of the timing requirement during fault interruption, overvoltage phenomenon, and ancillary mechanical support issues during EIS control is discussed,so as to implement the proposed EIS control properly for fast fault current suppression.

Particle Swarm Optimization-Support Vector Machine Model for Machinery Fault Diagnoses in High-Voltage Circuit Breakers

According to statistic data,machinery faults contribute to largest proportion of High-voltage circuit breaker failures,and traditional maintenance methods exist some disadvantages for that issue.Therefore,based on the wavelet packet decomposition approach and support vector machines,a new diagnosis model is proposed for such fault diagnoses in this study.The vibration eigenvalue extraction is analyzed through wavelet packet decomposition,and a four-layer support vector machine is constituted as a fault classifier.The Gaussian radial basis function is employed as the kernel function for the classifier.The penalty parameter c and kernel parameterδof the support vector machine are vital for the diagnostic accuracy,and these parameters must be carefully predetermined.Thus,a particle swarm optimizationsupport vector machine model is developed in which the optimal parameters c andδfor the support vector machine in each layer are determined by the particle swarm algorithm.The validity of this fault diagnosis model is determined with a real dataset from the operation experiment.Moreover,comparative investigations of fault diagnosis experiments with a normal support vector machine and a particle swarm optimization back-propagation neural network are also implemented.The results indicate that the proposed fault diagnosis model yields better accuracy and e-ciency than these other models.

FAULT DETECTION FOR MULTIPLE-VALUED LOGIC CIRCUITS WITH FANOUT-FREE

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.

Analysis on the fault characteristics of three-phase short-circuit for half-wavelength AC transmission lines

Half-wavelength AC transmission(HWACT) is an ultra-long distance AC transmission technology, whose electrical distance is close to half-wavelength at the system power frequency. It is very important for the construction and operation of HWACT to analyze its fault features and corresponding protection technology. In this paper, the steady-state voltage and current characteristics of the bus bar and fault point and the steady-state overvoltage distribution along the line will be analyzed when a three-phase symmetrical short-circuit fault occurs on an HWACT line. On this basis, the threephase fault characteristics for longer transmission lines are also studied.

A FAULT DETECTION SENSOR FOR CIRCUIT AGING USING DOUBLE-EDGE-TRIGGERED FLIP-FLOP

In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Double-edge-triggered Detection Sensor for circuit Aging (DSDA) is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not sensitive to the process variations. The worst case of the detection precision is more than 80% under the different process variations. It can detect aging fault effectively with the 8% power cost and 30% performance cost.

Wavelet neural network based fault diagnosis in nonlinear analog circuits

The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studied. Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the signature dada. The best wavelet function is selected based on the between-category total scatter of signature. The fault dictionary of nonlinear circuits is constructed based on improved back-propagation(BP) neural network. Experimental results demonstrate that the method proposed has high diagnostic sensitivity and fast fault identification and deducibility.

Robust Fault Diagnosis of Analog Circuits with Tolerances

A method for robust analog fault diagnosis using hybrid neural networks is proposed. The primary focus of the paper is to provide robust diagnosis using a mechanism to deal with the problem of element tolerances and reduce testing time. The proposed approach is based on the fault dictionary diagnosis method and backward propagation neural network (BPNN) and the adaptive resonance theory (ART) neural network. Simulation results show that the method is robust and fast for fault diagnosis of analog circuits with tolerances.

Testing Cross-Talk Induced Delay Faults in Digital Circuit Based on Transient Current Analysis

The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.

THE EFFECTIVE RANGE OF K-FAULT DIAGNOSIS OF-LINEAR CIRCUITS

In view of K-fault testability,the topological construction of a practical circuitis far from ideal.In order to improve the testability of a circuit,we may increase the numberof accessible nodes or use the multi-excitation method.Effectiveness of these methods and thefeasibility of choosing accessible nodes are discussed in detail.The conditions for multi-excitationtestability are presented.