Undesirable audio click and pop may be generated in a speaker or headphone.Compared to linear（class A/B/AB） amplifiers,class D amplifiers that comprise of an input stage and a modulation stage are more prone to prod...Undesirable audio click and pop may be generated in a speaker or headphone.Compared to linear（class A/B/AB） amplifiers,class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop.This article analyzes sources that generate click and pop in class D amplifiers,and corresponding ways to suppress them.For a class D amplifier with a single-ended input,click and pop is likely to be due to two factors.One is from a voltage difference（KDIF） between the voltage of an input capacitance（Vcin） and a reference voltage（Vref） of the input stage,and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents（BFVC） of the modulation stage.In this article,a fast charging loop is introduced into the input stage to charge F_（CIN） to roughly near VREF.Then a correction loop further charges or discharges V_（CIN）,substantially equalizing it with KREF.Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC,and the power switches are disabled until the BFVC are set up successfully.A two channel single-ended class D amplifier with the above features is fabricated with 0.5μm Bi-CMOS process.Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop.展开更多
This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of ...This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation. The prototype class D amplifier realized in 0.35 μm digital technology achieves a THD＋N of 0.02% when delivering 400 m W to an 8 Ω load from V_（DD） =3.6 V. The PSRR of the prototype class D amplifier is 80 dB at217 Hz. Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost. In addition the prototype class D amplifier can operate in large voltage range with V_（DD）range from 2.5 to 4.2V in mobile application. The total area of the amplifier is 1.7mm^2.展开更多
This paper investigates the noise sources in a single-ended class D amplifier（SECDA） and suggests corresponding ways to lower the noise.The total output noise could be expressed as a function of the gain and noises ...This paper investigates the noise sources in a single-ended class D amplifier（SECDA） and suggests corresponding ways to lower the noise.The total output noise could be expressed as a function of the gain and noises from different sources.According to the function,the bias voltage（V_B） is a primary noise source,especially for a SECDA with a large gain.A low noise SECDA is obtained by integrating a filter into the SECDA to lower the noise of the V_B.The filter utilizes an active resister and an 80 pF capacitance to get a 3 Hz pole.A noise test and fast Fourier transform analysis show that the noise performance of this SECDA is the same as that of a SECDA with an external filter.展开更多
A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load...A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load. Its output dynamic range exceeds 100dB. The circuit is implemented with a TSMC 0. 18μm process. The die area is 0. 28mme. The supply voltage is 1. gV for the digital part and 3.3V for class D.展开更多
文摘Undesirable audio click and pop may be generated in a speaker or headphone.Compared to linear（class A/B/AB） amplifiers,class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop.This article analyzes sources that generate click and pop in class D amplifiers,and corresponding ways to suppress them.For a class D amplifier with a single-ended input,click and pop is likely to be due to two factors.One is from a voltage difference（KDIF） between the voltage of an input capacitance（Vcin） and a reference voltage（Vref） of the input stage,and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents（BFVC） of the modulation stage.In this article,a fast charging loop is introduced into the input stage to charge F_（CIN） to roughly near VREF.Then a correction loop further charges or discharges V_（CIN）,substantially equalizing it with KREF.Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC,and the power switches are disabled until the BFVC are set up successfully.A two channel single-ended class D amplifier with the above features is fabricated with 0.5μm Bi-CMOS process.Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop.
基金supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044)
文摘This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation. The prototype class D amplifier realized in 0.35 μm digital technology achieves a THD＋N of 0.02% when delivering 400 m W to an 8 Ω load from V_（DD） =3.6 V. The PSRR of the prototype class D amplifier is 80 dB at217 Hz. Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost. In addition the prototype class D amplifier can operate in large voltage range with V_（DD）range from 2.5 to 4.2V in mobile application. The total area of the amplifier is 1.7mm^2.
文摘This paper investigates the noise sources in a single-ended class D amplifier（SECDA） and suggests corresponding ways to lower the noise.The total output noise could be expressed as a function of the gain and noises from different sources.According to the function,the bias voltage（V_B） is a primary noise source,especially for a SECDA with a large gain.A low noise SECDA is obtained by integrating a filter into the SECDA to lower the noise of the V_B.The filter utilizes an active resister and an 80 pF capacitance to get a 3 Hz pole.A noise test and fast Fourier transform analysis show that the noise performance of this SECDA is the same as that of a SECDA with an external filter.
文摘目的 探讨血D-二聚体(D-dimer,D-D)联合白细胞计数(white blood cell count, WBC)对评估肝硬化Child-Pugh A级患者急性症状性门静脉血栓(portal vein thrombosis, PVT)治疗效果的临床价值。方法 回顾性分析2015年1月至2022年12月在首都医科大学附属北京世纪坛医院干部综合科治疗的128例肝硬化患者的相关临床数据。最终选取18例Child-Pugh A级急性症状性PVT经抗凝治疗后血管再通的患者纳入研究。按抗凝治疗方案的不同,分为低分子肝素组,华法林组和利伐沙班组,比较3组患者PVT抗凝治疗前后的血常规、凝血四项+D-D、肝肾功的结果差异。结果 (1)3组患者的D-D分别在急性症状性PVT时及抗凝治疗血管再通后差异有统计学意义(低分子肝素组:9.01±1.17 vs 1.27±0.65,P<0.001;华法林组:9.28±1.78 vs 1.50±0.31,P<0.001;利伐沙班组:7.04±1.44 vs 1.32±0.32,P<0.01)。(2)3组患者的WBC分别在急性症状性PVT时及抗凝治疗血管再通后差异有统计学意义(低分子肝素组:6.82±0.95 vs 4.50±0.51,P<0.05;华法林组:7.28±0.91 vs 3.99±0.37,P<0.01;利伐沙班组:7.49±1.02 vs 4.43±0.62,P<0.05)。(3)3组患者的其他指标如红细胞计数,血红蛋白等分别在急性症状性PVT时及抗凝治疗血管再通后差异无统计学意义(P>0.05)。(4)PVT时,各组的D-D或者WBC差异无统计学意义;PVT抗凝治疗血管再通后各组的D-D或者WBC差异也无统计学意义(P>0.05)。其他指标如,ALT、AST等差异也无统计学意义(P>0.05)。结论 D-D与WBC分别在肝硬化Child-Pugh A级患者急性症状性PVT时及抗凝治疗血管再通后差异有统计学意义,这两个指标可用于评估PVT抗凝治疗时是否实现血管再通。临床实践中,联合这两个指标可能直接用于评估PVT抗凝治疗后血管是否再通。
文摘A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load. Its output dynamic range exceeds 100dB. The circuit is implemented with a TSMC 0. 18μm process. The die area is 0. 28mme. The supply voltage is 1. gV for the digital part and 3.3V for class D.
