Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embed...Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD＋N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 pA, The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm^2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.展开更多
This paper describes a multimode high-resolution digital pulse width modulator.This modulator,based on a novel hybrid structure,not only has a programmable duty cycle but also realizes phase modulation.A 576 ps pulse ...This paper describes a multimode high-resolution digital pulse width modulator.This modulator,based on a novel hybrid structure,not only has a programmable duty cycle but also realizes phase modulation.A 576 ps pulse resolution is achieved based on a 13.56 MHz switching frequency for near field communication.Fabricated in a SMIC 0.18-μm EEPROM CMOS process,the total area of modulator is only 130×180μm2.Measurement results validate the multi-mode modulation function and high pulse resolution.展开更多
A digital input class-D audio amplifier with a sixth-order pulse-width modulation （PWM） modulator is presented. This modulator moves the PWM generator into the closed sigma-delta modulator loop. The noise and distor...A digital input class-D audio amplifier with a sixth-order pulse-width modulation （PWM） modulator is presented. This modulator moves the PWM generator into the closed sigma-delta modulator loop. The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma-delta modulator. Therefore, at the output of the modulator, a very clean PWM signal is acquired for driving the power stage of the class-D amplifier. A sixth-order modulator is designed to balance the performance and the system clock speed. Fabricated in standard 0.18 μm CMOS technology, this class-D amplifier achieves 110 dB dynamic range, 100 dB signal-to-noise rate, and 0.0056% total harmonic distortion plus noise.展开更多
基金supported by the National Outstanding Young Scientist Foundation of China (No. 60725415)the National Natural ScienceFoundation of China (No. 60676009)+1 种基金the Doctor Foundation of Ministry of Education (No. 20050701015)the InnovationFunds (No. 07C26226101993).
文摘Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD＋N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 pA, The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm^2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.
基金Project supported by the Important National Science & Technology Specific Projects(No2009ZX03001-012-03)
文摘This paper describes a multimode high-resolution digital pulse width modulator.This modulator,based on a novel hybrid structure,not only has a programmable duty cycle but also realizes phase modulation.A 576 ps pulse resolution is achieved based on a 13.56 MHz switching frequency for near field communication.Fabricated in a SMIC 0.18-μm EEPROM CMOS process,the total area of modulator is only 130×180μm2.Measurement results validate the multi-mode modulation function and high pulse resolution.
基金supported by the National High Technology Research and Development Program of China(No.2012AA012301)the National Natural Science Foundation of China(No.61171001)
文摘A digital input class-D audio amplifier with a sixth-order pulse-width modulation （PWM） modulator is presented. This modulator moves the PWM generator into the closed sigma-delta modulator loop. The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma-delta modulator. Therefore, at the output of the modulator, a very clean PWM signal is acquired for driving the power stage of the class-D amplifier. A sixth-order modulator is designed to balance the performance and the system clock speed. Fabricated in standard 0.18 μm CMOS technology, this class-D amplifier achieves 110 dB dynamic range, 100 dB signal-to-noise rate, and 0.0056% total harmonic distortion plus noise.
文摘目的 探讨血D-二聚体(D-dimer,D-D)联合白细胞计数(white blood cell count, WBC)对评估肝硬化Child-Pugh A级患者急性症状性门静脉血栓(portal vein thrombosis, PVT)治疗效果的临床价值。方法 回顾性分析2015年1月至2022年12月在首都医科大学附属北京世纪坛医院干部综合科治疗的128例肝硬化患者的相关临床数据。最终选取18例Child-Pugh A级急性症状性PVT经抗凝治疗后血管再通的患者纳入研究。按抗凝治疗方案的不同,分为低分子肝素组,华法林组和利伐沙班组,比较3组患者PVT抗凝治疗前后的血常规、凝血四项+D-D、肝肾功的结果差异。结果 (1)3组患者的D-D分别在急性症状性PVT时及抗凝治疗血管再通后差异有统计学意义(低分子肝素组:9.01±1.17 vs 1.27±0.65,P<0.001;华法林组:9.28±1.78 vs 1.50±0.31,P<0.001;利伐沙班组:7.04±1.44 vs 1.32±0.32,P<0.01)。(2)3组患者的WBC分别在急性症状性PVT时及抗凝治疗血管再通后差异有统计学意义(低分子肝素组:6.82±0.95 vs 4.50±0.51,P<0.05;华法林组:7.28±0.91 vs 3.99±0.37,P<0.01;利伐沙班组:7.49±1.02 vs 4.43±0.62,P<0.05)。(3)3组患者的其他指标如红细胞计数,血红蛋白等分别在急性症状性PVT时及抗凝治疗血管再通后差异无统计学意义(P>0.05)。(4)PVT时,各组的D-D或者WBC差异无统计学意义;PVT抗凝治疗血管再通后各组的D-D或者WBC差异也无统计学意义(P>0.05)。其他指标如,ALT、AST等差异也无统计学意义(P>0.05)。结论 D-D与WBC分别在肝硬化Child-Pugh A级患者急性症状性PVT时及抗凝治疗血管再通后差异有统计学意义,这两个指标可用于评估PVT抗凝治疗时是否实现血管再通。临床实践中,联合这两个指标可能直接用于评估PVT抗凝治疗后血管是否再通。
