The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor netwo...The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.展开更多
For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchron...For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.展开更多
A 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） without dedicated front-end sampleand-hold amplifier（SHA） is presented. In addition to elaborate matching of the sampling network in the first stage,a b...A 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） without dedicated front-end sampleand-hold amplifier（SHA） is presented. In addition to elaborate matching of the sampling network in the first stage,a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18- m CMOS technology, the presented ADC occupies a chip area of 12 mm2, and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-d B signal-to-noise and distortion ratio（SNDR）,an 85.4-d B spurious-free dynamic range（SFDR）, a maximum differential nonlinearity（DNL） of 0.22 LSB and a maximum integral nonlinearity（INL） of 1.4 LSB.展开更多
基金the Hi-Tech Research and Development Program of China（2006AA01Z226）the Scientific Research Foundation of Huazhong University of Science and Technology（2006Z001B)the Natural Science Foundation of Hubei（2006ABA080）.
文摘The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.
基金Supported by the National Natural Science Foundation of China(No.11005107)Anhui University Natural Science Research(No.K J2010A334)
文摘For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.
基金Project supported by the National Natural Science Foundation of China(No.61474092)
文摘A 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） without dedicated front-end sampleand-hold amplifier（SHA） is presented. In addition to elaborate matching of the sampling network in the first stage,a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18- m CMOS technology, the presented ADC occupies a chip area of 12 mm2, and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-d B signal-to-noise and distortion ratio（SNDR）,an 85.4-d B spurious-free dynamic range（SFDR）, a maximum differential nonlinearity（DNL） of 0.22 LSB and a maximum integral nonlinearity（INL） of 1.4 LSB.
