A metastability-based TRNG（true random number generator） is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL（programmable delay line）.With ...A metastability-based TRNG（true random number generator） is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL（programmable delay line）.With the proposed coarse-tuning PDL structure, the TRNG core does not require extra placement and routing to ensure its entropy. Furthermore, the core needs fewer stages of coarse-tuning PDL at higher operating frequency,and thus saves more resources in FPGA. The designed TRNG achieves 25 Mbps @ 100 MHz throughput after proper post-processing, which is several times higher than other previous TRNGs based on FPGA. Moreover, the robustness of the system is enhanced with the adoption of a feedback system. The quality of the designed TRNG is verified by NIST（National Institute of Standards and Technology） and also accepted by class P1 of the AIS-20/31 test suite.展开更多
A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator...A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator（VCO）gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.展开更多
基金Project supported by the S&T Plan of Zhejiang Provincial Science and Technology Department(No.2016C31078)the National Natural Science Foundation of China(Nos.61574041,61474068,61234002)the K.C.Wong Magna Fund in Ningbo University,China
文摘A metastability-based TRNG（true random number generator） is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL（programmable delay line）.With the proposed coarse-tuning PDL structure, the TRNG core does not require extra placement and routing to ensure its entropy. Furthermore, the core needs fewer stages of coarse-tuning PDL at higher operating frequency,and thus saves more resources in FPGA. The designed TRNG achieves 25 Mbps @ 100 MHz throughput after proper post-processing, which is several times higher than other previous TRNGs based on FPGA. Moreover, the robustness of the system is enhanced with the adoption of a feedback system. The quality of the designed TRNG is verified by NIST（National Institute of Standards and Technology） and also accepted by class P1 of the AIS-20/31 test suite.
基金supported by the National 11th Five-Year Plan of China(No.51308020403)the Science and Technology Commission of Shanghai Municipality(No.08706200700)the National Hi-Tech Research and Development Program of China(No.2009AA01Z261).
文摘A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator（VCO）gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.
