Adding Pseudo-Random Test Sequence Generator in the Test Simulator for DFT Approach

This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.

Reduction of Faults in Software Testing by Fault Domination

Although mutation testing is one of the practical ways of enhancing test effectiveness in software testing, it could be sometimes infeasible in practical work for a large scale software so that the mutation testing becomes time-consuming and even in prohibited time. Therefore, the number of faults assumed to exist in the software under test should be reduced so as to be able to confine the time complexity of test within a reasonable period of time. This paper utilizes the concept of fault dominance and equivalence, which has long been employed in hardware testing, for revealing a novel way of reducing the number of faults assumed to hide in software systems. Once the number of faults assumed in software is decreased sharply, the effectiveness of mutation testing will be greatly enhanced and become a feasible way of software testing. Examples and experimental results are presented to illustrate the effectiveness and the helpfulness of the technology proposed in the paper.