A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high ...A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.展开更多
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z282)the National Natural Science Foundation of China(No.60876019)
文摘A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.
