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A self-biased PLL with low power and compact area 被引量:1
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作者 贾海珑 陈先敏 +1 位作者 刘琦 冯光涛 《Journal of Semiconductors》 EI CAS CSCD 2015年第10期130-134,共5页
A new low power, low phase jitter, compact realization, and sell-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced. The proposed self-biased PLL eliminates extra band gap biasing circuits, an... A new low power, low phase jitter, compact realization, and sell-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced. The proposed self-biased PLL eliminates extra band gap biasing circuits, and internally generates all the biasing voltages and currents. Meanwhile, all of the PLL dynamic loop parameters, such as loop bandwidth, natural frequency, damping factors are kept constant adaptively. By optimizing the circuit structures, the perfect unity of chip estate, power dissipation, phase jitter, and loop stability is achieved. THe PLL consumes 4.2 mW of power tinder 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency, while occupying a die area of less than 0.02 mmz (180 × 110 μm2), and the typical period jitter (RMS) is around 2.8 ps. 展开更多
关键词 self-biased PLL ring VCO low power compact area
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