Novel Design of Low-power Multiplex Differential Voltage Comparators

A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly.

A CMOS Dynamic Comparator for Pipelined ADCs with Improved Speed/Power Ratio

This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution. Because the architecture is based on the coupled current sources and differential input pairs, this comparator＇s threshold voltage can be adjusted to a desired level. Compared with traditional comparators, this one shows significant improvement in area,power,and speed. Fabricated in 0.35μm CMOS technology,it occupies only 30μm × 70μm. Simulation and measurement results indicate the comparator has a sampling frequency up to 1GHz with 2Vpp differential input signal range and only 181μW power consumption under a 3.3V supply. The speed/power ratio reaches up to 5524GS/J.

A Time-Domain Comparator Based Skipping-Window SAR ADC

This paper presents an energy efficient successive-approximation register(SAR)analog-to-digital converter(ADC)for low-power applications.To improve the overall energy-efficiency,a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator,which can provide not only the polarity of the input,but also the amount information of the input.The timedomain comparator,which is based on the edge pursing principle,consists of delay cells,two NAND gates,two D-flip-flop register-based phase detectors and a counter.The digital characteristic of the comparator makes the design more flexible,and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number.An energy efficient digital-to-analog converter(DAC)control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion.Together with the skipping-window technique,the linearity and the power consumption of the SAR ADC are improved.The impact of different window sizes on comparison cycles,DAC switching energy and the overall energy efficiency is analyzed.Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC,as well as the linearity,and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.

A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs

The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.

THE DESIGN OF THE HIGH SPEED AND HIGH PRECISION LATCHING VOLTAGE COMPARATOR ZJ03

The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03.

Single-Bit Comparator in Quantum-Dot Cellular Automata (QCA) Technology Using Novel QCAXNOR Gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an option nowadays and other technologies need to be investigated.The quantum-dot cellular automata(QCA)technology is one of the important emerging nanotechnologies that have attracted much researchers’attention in recent years.This technology has many interesting features,such as high speed,low power consumption,and small size.These features make it an appropriate alternative to the CMOS technique.This paper suggests three novel structures of XNOR gates in the QCA technology.The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology.The proposed structures are used as the main building blocks for a single-bit comparator.The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature.The comparison results are encouraging to append the proposed structures to the library of QCA gates.

A Two-Dimension Time-Domain Comparator for Low Power SAR ADCs

This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register(SAR)analog-to-digital converters(ADCs).The proposed two-dimension time-domain comparator consists of a ring oscillator collapse-based comparator and a counter.The propagation delay of a voltage controlled ring oscillator depends on the input.Thus,the comparator can automatically change the comparison time according to its input difference,which can adjust the power consumption of the comparator dynamically without any control logic.And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small.Thus,the proposed comparator can not only provide the polarity of the input,but also the amount information of the input,which helps to skip most of the SAR cycles when the initial input is small.Thus,most energy can be saved when the initial input is small.The proposed time-domain comparator is designed in 0.18μm CMOS technology.Simulation results demonstrate that the comparator can not only save power consumption,but also give the design flexibility,and the current is only nA level when the supply voltage is 0.6 V.

Design of Low Power Comparator Using DG Gate

In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.

Analysis on the Magnetic Shielding Effectiveness of DC Current Comparator

There are magnetic interference problems in the applications of DC current comparator. Analysis on the magnetic effectiveness which is applied by the external magnetic field is introduced in this paper. The effectiveness is proved by the actual results which are compared with the magnetic- circuit method and the finite element method. In addition, the reference comment is given which can be used in the practical work of DC current comparator shield design.

A 20-GHz ultra-high-speed InP DHBT comparator

An ultra-high-speed, master-slave voltage comparator circuit is designed and fabricated using InP/GaInAs double heterojunction bipolar transistor technology with a current gain cutoff frequency of 170 GHz. The complete chip die, including bondpads, is 0.75 × 1.04 mm22. It consumes 440 mW from a single M V power supply, excluding the clock part. 77 DHBTs have been used in the monolithic comparator. A full Nyquist test has been performed up to 20 GHz, with the input sensitivity varying from 6 mV at l0 GHz to 16 mV at 20 GHz. To our knowledge, this is the first InP based integrated circuit including more than 70 DHBTs, and it achieves the highest sampling rate found on the mainland of China.

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600μV at 16 MHz, and dissipates only 78μW of power dissipation at 5 V. The size of the chip is 210 × 180μm^2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.

Comparative transcriptome analysis between rhesus macaques(Macaca mulatta) and crab-eating macaques(M. fascicularis)

Understanding gene expression variations between species is pivotal for deciphering the evolutionary diversity in phenotypes. Rhesus macaques(Macaca mulatta, MMU)and crab-eating macaques(M. fascicularis, MFA) serve as crucial nonhuman primate biomedical models with different phenotypes. To date, however, large-scale comparative transcriptome research between these two species has not yet been fully explored. Here, we conducted systematic comparisons utilizing newly sequenced RNA-seq data from84 samples(41 MFA samples and 43 MMU samples)encompassing 14 common tissues. Our findings revealed a small fraction of genes(3.7%) with differential expression between the two species, as well as 36.5% of genes with tissue-specific expression in both macaques. Comparison of gene expression between macaques and humans indicated that 22.6% of orthologous genes displayed differential expression in at least two tissues. Moreover,19.41% of genes that overlapped with macaque-specific structural variants showed differential expression between humans and macaques. Of these, the FAM220A gene exhibited elevated expression in humans compared to macaques due to lineage-specific duplication. In summary,this study presents a large-scale transcriptomic comparison between MMU and MFA and between macaques and humans. The discovery of gene expression variations not only enhances the biomedical utility of macaque models but also contributes to the wider field of primate genomics.

超声辅助与纤维支气管镜辅助经皮扩张气管切开术的对比研究

目的探讨超声辅助经皮扩张气管切开术的应用价值。方法回顾性分析2020年12月~2022年12月在甘肃省人民医院重症医学科行经皮扩张气管切开术患者56例,均经口气管插管后呼吸机辅助呼吸,根据不同的辅助方式分为超声辅助(超声组)31例和纤维支气管镜辅助(纤维支气管镜组)25例。结果与纤维支气管镜组比较,超声组术中氧合指数(PaO_(2)/FiO_(2))增高[(157.3±19.2)mmHg vs.(145.4±22.8)mmHg,t=2.117,P=0.039],分钟通气(MV)量增高[(7.3±0.8)L/min vs.(6.1±0.7)L/min,t=5.278,P<0.001],动脉血二氧化碳分压(PCO_(2))降低[(39.1±4.8)mmHgvs.(44.3±5.6)mmHg,t=-3.709,P<0.001],术后出血例数减少[0例vs.4例,χ^(2)=5.246,P=0.022]。结论超声组较纤维支气管镜组行经皮扩张气管切开术手术并发症少,安全性高。

低温等离子射频消融联合下鼻甲骨折外移术治疗阻塞性睡眠呼吸暂停低通气综合征的疗效观察

目的探讨阻塞性睡眠呼吸暂停低通气综合征(OSAHS)患者接受低温等离子射频消融联合下鼻甲骨折外移术后睡眠及经鼻持续气道正压通气(nasal continuous positive airway pressure,nCPAP)治疗耐受性的改善情况。方法选择40例OSAHS合并双侧下鼻甲肥大的患者作为研究对象,均在局麻下接受下鼻甲低温等离子射频消融联合骨折外移术。术前及术后2周分别采用多导睡眠监测(PSG)、鼻阻力仪、autoCPAP呼吸机及视觉模拟量表(VAS)测定睡眠呼吸暂停低通气指数(AHI)、最低血氧饱和度(lowest oxygen saturation,LSaO_(2))、鼻气道阻力及nCPAP治疗耐受性。结果与术前比较,术后2周时患者AHI降低至(35.17±9.72)次/h,LSaO_(2)提高至(83.21±6.58)%,鼻气道阻力降低至(0.55±0.09)kPa·s/cm^(3),VAS评分升高至8.32±1.17,差异比较均有统计学意义(P均<0.05)。结论低温等离子射频消融联合下鼻甲骨折外移术能有效降低OSAHS患者的鼻阻力,提高nCPAP治疗的耐受性,改善OSAHS患者的睡眠情况。

A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator

A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters （ADCs） has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing time.This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage.Additionally,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference voltage.This proposed comparator with two traditional comparators has been realized by SMIC 0.13μm CMOS technology.The contrast experimental results verify these advantages over conventional comparators.It has been used in a 12-bit 100-MS/s pipeline ADC.

An offset cancellation technique in a switched-capacitor comparator for SAR ADCs

An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB

This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.

Comparative Orotomy of the Archean Superior,North China,and Phanerozoic Altaid Orogenic Systems Architecture

Geological maps encode vast amounts of data about rock types,ages,chemistry,orogenic architecture and deep-time history or different tectonic units,yet these are often difficult to extract because of the way different geologists portray their results at various scales.To understand orogenesis in 4D,it is essential to uniformly integrate map data,together with geophysical data and deep geochemical mapping(Wang et al.,2023).