A deep trench super-junction LDMOS with double charge compensation layer

A deep trench super-junction LDMOS with double charge compensation layer(DC DT SJ LDMOS)is proposed in this paper.Due to the capacitance effect of the deep trench which is known as silicon-insulator-silicon(SIS)capacitance,the charge balance in the super-junction region of the conventional deep trench SJ LDMOS(Con.DT SJ LDMOS)device will be broken,resulting in breakdown voltage(BV)of the device drops.DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con.DT SJ LDMOS device.Therefore,the drift region reaches an ideal charge balance state again.The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply,meanwhile the enlarged on-current region reduces its specific on-resistance.The simulation results show that compared with the Con.DT SJ LD-MOS,the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V,and the R_(on,sp) decreased to 23.7 mΩ·cm^(2).

Barrier and compensation layers in the East China Sea

Climatology of the isothermal layer depth （ILD） and the mixed layer depth （MLD） has been produced from in-situ temperaturesalinity observations in the East China Sea （ECS） since 1925. The methods applied on the global are used to compute the ILD and the MLD in the ECS with a temperature criterion AT=0. 8 ℃ for the ILD, and a density criterion with a threshold △σθ corresponding to fixed △T=0. 8 ℃ for the MLD, respectively. With the derived climatology ILD and MLD, the monthly variations of the barrier layer （BL） and the compensation layer （CL） in the ECS are analyzed. The BL mainly exists in the shallow water region of the ECS during April-June with thickness larger than 15 m. From December to next March, the area along the shelf break from northeast of Taiwan Island to the northeast ECS is characterized by the CL. Two kinds of main temperature - salinity structures of the CL in this area are given.

Impact of GaNAs strain compensation layer on the electronic structure of InAs/GaAs quantum dots

The strain and electron energy levels of InAs/GaAs（001） quantum dots （QDs） with a GaNAs strain compensation layer （SCL） are investigated. The results show that both the hydrostatic and biaxiai strain inside the QDs with a GaNAs SCL are reduced compared with those with GaAs capping layers. Moreover, most of the compressive strain in the growth surface is compensated by the tensile strain of the GaNAs SCL, which implies that the influence of the strain environment of underlying QDs upon the next-layer QDs＇ growth surface is weak and suggests that the homogeneity and density of QDs can be improved. Our results are consistent with the published experimental literature. A GaNAs SCL is shown to influence the strain and band edge. As is known, the strain and the band offset affect the electronic structure, which shows that the SCL is proved to be useful to tailor the emission wavelength of QDs. Our research helps to better understand how the strain compensation technology can be applied to the growth of stacked QDs, which are useful in solar cells and laser devices.

A high-voltage SOI MOSFET with a compensation layer on the trenched buried oxide layer

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.