A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplific...A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.展开更多
With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper first...With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.展开更多
A fully integrated CMOS differential power amplifier driver（PAD） is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the outpu...A fully integrated CMOS differential power amplifier driver（PAD） is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the output matching network.A differential inductance constitutes an inter-stage matching network.Meanwhile,an on chip balun realizes input matching as well as single-end to differential conversion.The PAD is fabricated in a 0.13μm RFCMOS process.The chip size is 1.1×1.1 mm^2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.展开更多
Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field ...Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.展开更多
A novel pulse stream neuron circuit is presented whose output pulse width facilitates sigmoid activation to activate the function of neurons. The wide symmetrical dynamic range of this neuron ensures high noise immuni...A novel pulse stream neuron circuit is presented whose output pulse width facilitates sigmoid activation to activate the function of neurons. The wide symmetrical dynamic range of this neuron ensures high noise immunity. The pulsed activation strategy provides a power efficient architecture, so the circuit has very low power dissipation. The simplicity of the circuit ensures its suitability for large-scale integration.展开更多
基金The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2A7)
文摘A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.
基金supported by the National Natural Science Foundations of China (Nos. 61306030, 61674037)the National Key R&D Program of China (Nos.2016YFC0800400, 2018YFE0205900)the National Science and Technology Major Project (No. 2018ZX03001008)
文摘With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.
文摘功率放大器PA(Power Amplifier)是射频前端重要的模块,基于SMIC 55 nm RF CMOS工艺,设计了一款60 GHz两级差分功率放大器。针对毫米波频段下,硅基CMOS晶体管栅漏电容(C_(gd))严重影响放大器的增益和稳定性的问题,采用交叉耦合电容中和技术抵消C_(gd)影响。通过优化级间匹配网络和有源器件参数,提高了功率放大器的输出功率,增益和效率。后仿结果显示,在1.2 V的供电电压下,工作在60 GHz的功率放大器饱和输出功率为11.3 d Bm,功率增益为16.2 d B,功率附加效率为17.0%,功耗为62 m W。芯片面积380μm×570μm。
基金Project supported by the National Natural Science Foundation of China(No.61106025)the National High Technology Research and Develop Program of China(No.2012AA012301)
文摘A fully integrated CMOS differential power amplifier driver（PAD） is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the output matching network.A differential inductance constitutes an inter-stage matching network.Meanwhile,an on chip balun realizes input matching as well as single-end to differential conversion.The PAD is fabricated in a 0.13μm RFCMOS process.The chip size is 1.1×1.1 mm^2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.
文摘Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.
基金Supported by the National Natural Science Foundationof China (No.6963 60 3 0)
文摘A novel pulse stream neuron circuit is presented whose output pulse width facilitates sigmoid activation to activate the function of neurons. The wide symmetrical dynamic range of this neuron ensures high noise immunity. The pulsed activation strategy provides a power efficient architecture, so the circuit has very low power dissipation. The simplicity of the circuit ensures its suitability for large-scale integration.
