典型CMOS器件总剂量加速试验方法验证

应用美军标试验方法1019.5和1019.4分别对两种典型(ComplementaryMetal?Oxide?SemiconductorTransistor,CMOS)器件进行试验验证,论述了试验原理,对试验现象进行了详细的分析,了解实验室条件下评估空间氧化物陷阱电荷和界面陷阱电荷的可行性和保守性。实验表明,两种不同工艺的CC4069器件没有通过1019.5所做出的试验验证,从实验现象观察认为是由于界面陷阱电荷大量建立所引起的。加固LC4007?RHANMOS却通过了与1019.5相比过分保守的1019.4的试验验证。

A CMOS high-IF down-conversion mixer for WLAN 802.11a applications

A low noise, high conversion gain down-conversion mixer for WLAN 802.11a applications, which adopts the high intermediate frequency （IF） topology, is presented. The input radio frequency （RF）band, local oscillator（LO）frequency band and output IF are 5.15 to 5.35, 4.15 to 4.35 and 1 GHz, respectively. Source resistive degeneration technique and pseudo-differential Gilbert topology are used to achieve high linearity, and, current bleeding technique and LC resonant loads are used to acquire a low noise figure. In addition, the mixer adopts a common-source transistor pair cross-stacked with a source follow pair（CSSF）circuit as an output buffer to enhance the mixer＇s conversion gain but not deteriorate the other performances. The mixer is implemented in 0.18 μm RF CMOS（complementary metal oxide semiconductor transistor）technology and the chip area of the mixer including all bonding pads is 580 μm×1 185 μm. The measured results show that under a 1.8 V supply, the conversion gain is 10.1 dB; the input 1 dB compression point and the input-referred third-order intercept point are-3.5 and 5.3 dBm, respectively; the single side band （SSB）noise figure （NF）is 8.65 dB, and the core current consumption is 3.8 mA.

基于CMOS工艺的太赫兹探测器

提出了一种新型多频太赫磁探测器电路结构,采用圆形、菱形以及环形天线嵌套式构成多频探测单元,四个探测器相互之间设计保护层包围隔离,防止外部电路对其影响。在高频结构仿真器（HFSS）下对设计的双环差分天线、单环差分天线、圆形开槽天线和菱形天线进行模型与特性参数仿真优化。基于TSMC CMOS 0.18μm工艺制备了多频太赫兹探测器芯片,该芯片能实现280,290,320,600和806 GHz多频段探测功能。测试结果表明,双环天线结构、圆形开槽天线结构、菱形天线结构和单环差分天线结构的探测器在阈值电压为0.42 V时,最佳响应度分别为366.6,1 286.6,366.3和701.2 V/W,最小噪声等效功率分别为0.578,0.211,0.594和0.261 nW√Hz。

10 Gbit/s 0.25μm CMOS 1∶4 demultiplexer

A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.

Design of CMOS class-E power amplifier for low power applications

A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.

基于TMD材料的CMOS反相器电路研究现状

对目前基于过渡金属硫族化合物(TMD)材料(MoS_(2)、WSe_(2)等)的互补金属氧化物半导体(CMOS)反相器电路相关研究进行了综述。总结了TMD材料的物理性质、制备方法和基于TMD的场效应晶体管器件的研究进展。对基于TMD的集成电路技术研究进行了介绍与分析。分别在结构设计、集成工艺、性能优化及电路集成等方面对基于TMD材料的CMOS反相器电路进行了总结与分析。介绍了两种集成结构及对应的工艺流程,详细分析了CMOS反相器电路性能优化的方法。最后指出了目前的关键挑战及未来的发展趋势。

Analysis of proton and γ-ray radiation effects on CMOS active pixel sensors

Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology. Two samples have been irradiated un-biased by 23 MeV protons with fluences of 1.43 × 10^11 protons/cm^2 and 2.14 × 10^11 protons/cm-2,respectively, while another sample has been exposed un-biased to 65 krad（Si） ^60Co γ-ray. The influences of radiation on the dark current, fixed-pattern noise under illumination, quantum efficiency, and conversion gain of the samples are investigated. The dark current, which increases drastically, is obtained by the theory based on thermal generation and the trap induced upon the irradiation. Both γ-ray and proton irradiation increase the non-uniformity of the signal, but the nonuniformity induced by protons is even worse. The degradation mechanisms of CMOS APS image sensors are analyzed,especially for the interaction induced by proton displacement damage and total ion dose（TID） damage.

一种阵列式版图布局的低温度系数CMOS带隙基准电压源

设计了一款低温度系数的自偏置CMOS带隙基准电压源电路,分析了输出基准电压与关键器件的温度依存关系,实现了低温度系数的电压输出。后端物理设计采用多指栅晶体管阵列结构进行对称式版图布局,以压缩版图面积。基于65 nm/3.3 V CMOS RF器件模型,在Cadence IC设计平台进行原理图和电路版图设计,并对输出参考电压的精度、温度系数、电源抑制比(PSRR)和功耗特性进行了仿真分析和对比。结果表明,在3.3 V电源和27℃室温条件下,输出基准电压的平均值为765.7 mV,功耗为0.75μW;在温度为-55~125℃时,温度系数为6.85×10~(-6)/℃。此外,输出基准电压受电源纹波的影响较小,1 kHz时的PSRR为-65.3 dB。

Wafer-scale carbon-based CMOS PDK compatible with siliconbased VLSI design flow

Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,encompassing materials and device technology,have enabled the fabrication of circuits with over 1000 gates,marking carbon-based integrated circuit design as a burgeoning field of research.A critical challenge in the realm of carbon-based very-large-scale integration(VLSI)is the lack of suitable automated design methodologies and infrastructure platforms.In this study,we present the development of a waferscale 3μm carbon-based complementary metal-oxide-semiconductor(CMOS)process design kit(PDK)(3μm-CNTFETs-PDK)compatible with silicon-based Electronic Design Automation(EDA)tools and VLSI circuit design flow.The proposed 3μm-CNTFETs-PDK features a contacted gate pitch(CGP)of 21μm,a gate density of 128 gates/mm^(2),and a transistor density of 554 transistors/mm^(2),with an intrinsic gate delay around 134 ns.Validation of the 3μm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits.Leveraging the carbon-based PDK and a silicon-based design platform,we successfully implemented a complete 64-bit static random-access memory(SRAM)circuit system for the first time,which exhibited timing,power,and area characteristics of clock@10 kHz,122.1μW,3795μm×2810μm.This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow,thereby laying the groundwork for future carbon-based VLSI advancements.

Wafer-scale fabrication of carbon-nanotube-based CMOS transistors and circuits with high thermal stability

Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication processes enable three-dimensional(3D)integration with logic and memory(static random access memory(SRAM),magnetic random access memory(MRAM),resistive random access memory(RRAM),etc.)to realize efficient near-memory computing.Importantly,carbon nanotube transistors require good thermal stability up to 400℃ processing temperature to be compatible with back-end-of-line(BEOL)process,which has not been previously addressed.In this work,we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity,where AlN was employed as electrostatic doping layer.The gate stack and passivation layer were optimized to realize high-quality interfaces.Specifically,we demonstrate 1-bit carbon nanotube full adders working under 250℃ with rail-to-rail outputs.

Air-stable n-type transistors based on assembled aligned carbon nanotube arrays and their application in complementary metal-oxide-semiconductor electronics

Carbon nanotubes(CNTs)are ideal candidates for beyond-silicon nano-electronics because of their high mobility and low-cost processing.Recently,assembled massively aligned CNTs have emerged as an important platform for semiconductor electronics.However,realizing sophisticated complementary nano-electronics has been challenging due to the p-type nature of carbon nanotubes in air.Fabrication of n-type behavior field effect transistors(FETs)based on assembled aligned CNT arrays is needed for advanced CNT electronics.Here in this paper,we report a scalable process to make n-type behavior FETs based on assembled aligned CNT arrays.Air-stable and high-performance n-type behavior CNT FETs are achieved with high yield by combining the atomic layer deposition dielectric and metal contact engineering.We also systematically studied the contribution of metal contacts and atomic layer deposition passivation in determining the transistor polarity.Based on these experimental results,we report the successful demonstration of complementary metal-oxide-semiconductor inverters with good performance,which paves the way for realizing the promising future of carbon nanotube nano-electronics.

Neuronal signal detecting and stimulating circuit array for monolithic integrated MEA

A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operational amplifier） is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to ＋ 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.

纳电子学与神经形态芯片的新进展

综述了纳电子学和神经形态芯片进入新世纪后所处发展阶段以及近两年的最新进展。在纳电子领域,综述并分析了当今集成电路的发展现状,包括鳍式场效应晶体管（Fin FET）的发展、10 nm节点的技术突破、7 nm和5 nm节点的前瞻性技术研究以及三类后互补金属氧化物半导体（CMOS）器件（自旋电子器件、隧穿FET和碳纳米管栅的二维半导体Mo S2晶体管）的探索性研究,指出摩尔定律将沿着加强栅对沟道电子的控制（三栅和环栅）、更换高迁移率材料和采用新机理等技术路线继续前行。在神经形态芯片领域,综述并分析了神经形态芯片的发展历程、＂真北＂类脑芯片的技术创新和应用、当今嵌入式神经处理器的四个发展特点和采用新器件提高能量效率的探索。采用纳电子技术的神经形态芯片的发展将成为未来智能时代发展的基础。

InGaAs纳电子学的进展

InGaAs HEMT器件和纳米加工技术的结合推动了InGaAs纳电子学的发展,在太赫兹和后CMOS逻辑电路两大领域产生重要影响。综述了InGaAs纳电子学近10年在两大领域的发展路径和最新进展。在太赫兹领域,InGaAs纳电子学以InGaAs HEMT发展为主,沿着提高沟道In组分、缩小T型栅长、减少势垒层厚度和寄生电阻的技术路线发展。InGaAs太赫兹单片集成电路(TMIC)的工作频率达到1 THz,成为目前工作频率最高的晶体管。在后CMOS逻辑电路领域,InGaAs纳电子学以InGaAs MOSFET发展为主,沿着提高复合量子阱沟道中的In组分、缩小平面器件结构中的栅长、缩小立体器件结构中的鳍宽、减少埋栅结构中复合高k介质栅厚度、减少寄生电阻和在大尺寸Si晶圆上与Ge MOSFET共集成的技术路线发展。鳍宽为30 nm的InGaAs FinFET的亚阈值斜率(SS)为82 mV/dec,漏感生势垒降低(DIBL)为10 mV/V,最大跨导(g_(m,max))为1.8 mS/μm,导通电流(I_(ON))为0.41 mA/μm,关断电流(I_(OFF))为0.1μA/μm,其性能优于同尺寸的Si FinFET,具有成为后CMOS的7 nm节点后替代NMOSFET器件的潜力。

一种新型Rail-to-Rail运算放大器的设计与分析

提出了一种采用线性跨导输入级的Rail-to-Rail运算放大器,输入级的跨导基本实现了与共模输入电压无关,而只与工艺参数和工作电压有关。采用了复合晶体管的设计,使等效NMOS和等效PMOS的电学参数一致,摈弃了由于PMOS及NMOS的不一致性而采取的补偿措施,输出级采用甲乙类CMOS结构。

Ka-band ultra low voltage miniature sub-harmonic resistive mixer with a new broadside coupled Marchand balun in 0.18-μm CMOS technology

A Ka-band sub-harmonically pumped resistive mixer （SHPRM） was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor （CMOS） technology. An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance （balun） with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation （LO） signal from single to differential mode. The results showed that the SHPRM achieves the conversion gain of -15- -12.5 dB at fixed fIF=0.5 GHz with 8 dBm LO input power for the radio frequency （RF） bandwidth of 28 35 GHz. The in-band LO-intermediate freqency （IF）, RF-IF, and LO-RF isolations are better than 31, 34, and 36 dB, respectively. Besides, the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB, respectively. The measured input referred PIdB and 3rd-order inter-modulation intercept point （IIP3） are 0.5 and 10.5 dBm, respectively. The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm^2 including pads.

Strain induced changes in performance of strained-Si/strained-Si1-yGey/relaxed-Si1-xGex MOSFETs and circuits for digital applications

Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.

DC Gain Analysis of Scaled CMOS Op Amp in Sub-100 nm Technology Nodes:A Research Based on Channel Length Modulation Effect

Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.

Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Multi-threshold complementary metal-oxide- semiconductor （MTCMOS） is ofbn used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode （sleep-to-active） is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45nm CMOS technology.

Visible-blind short-wavelength infrared photodetector with high responsivity based on hyperdoped silicon

Developing a low-cost, room-temperature operated and complementary metal-oxide-semiconductor(CMOS)compatible visible-blind short-wavelength infrared(SWIR) silicon photodetector is of interest for security,telecommunications, and environmental sensing. Here, we present a silver-supersaturated silicon(Si:Ag)-based photodetector that exhibits a visible-blind and highly enhanced sub-bandgap photoresponse. The visible-blind response is caused by the strong surface-recombination-induced quenching of charge collection for short-wavelength excitation, and the enhanced sub-bandgap response is attributed to the deep-level electrontraps-induced band-bending and two-stage carrier excitation. The responsivity of the Si:Ag photodetector reaches 504 mA · W^(-1) at 1310 nm and 65 m A · W^(-1) at 1550 nm under-3 V bias, which stands on the stage as the highest level in the hyperdoped silicon devices previously reported. The high performance and mechanism understanding clearly demonstrate that the hyperdoped silicon shows great potential for use in optical interconnect and power-monitoring applications.