Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial tr...Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.展开更多
The algorithm and its implementation of the leading zero anticipation （LZA） are very vital for the performance of a high-speed floating-point adder in today＇s state of art microprocessor design. Unfortunately, in p...The algorithm and its implementation of the leading zero anticipation （LZA） are very vital for the performance of a high-speed floating-point adder in today＇s state of art microprocessor design. Unfortunately, in predicting ＂shift amount＂ by a conventional LZA design, the result could be off by one position. This paper presents a novel parallel error detection algorithm for a general-case LZA. The proposed approach enables parallel execution of conventional LZA and its error detection, so that the error-indicatlon signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. The circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work.展开更多
文摘Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.
文摘The algorithm and its implementation of the leading zero anticipation （LZA） are very vital for the performance of a high-speed floating-point adder in today＇s state of art microprocessor design. Unfortunately, in predicting ＂shift amount＂ by a conventional LZA design, the result could be off by one position. This paper presents a novel parallel error detection algorithm for a general-case LZA. The proposed approach enables parallel execution of conventional LZA and its error detection, so that the error-indicatlon signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. The circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work.
