Development of hydraulic power unit and accumulator charging circuit for electricity generation,storage and distribution

It is the purpose of the present paper to convert hydraulic energy to electric energy and saves both the pressure and electrical energy for re - use during the next system upstroke using two secondary units coupled to induction motor to drive cylinder loads. During upstroke operation, the variable pump/motor （P/M） driven by both electric motor and the second （P/M） works as hydraulic pump and output flow to the cylinders which drive the load. During load deceleration, the cylinders work as pump while the operation of the two secondary units are reversed, the variable （P/M） works as a motor generating a torque with the electric motor to drive the other （P/M） which transforms mechanical energy to hydraulic energy that is saved in the accumulator. When the energy storage capacity of the accumulator is attained as the operation continues, energy storage to the accumulator is thermostatically stopped while the induction motor begins to work as a generator and generates electricity that is stored in the power distribution unit. Simulations were performed using a limited PT2 Block, i.e. 2nd-order transfer function with limitation of slope and signal output to determine suitable velocity of the cylinder which will match high performance and system stability. A mathematical model suited to the simulation of the hydraulic accumulator both in an open-or close-loop system is presented. The quest for improvement of lower energy capacity storage, saving and re-utilization of the conventional accumulator resulting in the short cycle time usage of hydraulic accumulators both in domestic and industrial purposes necessitates this research. The outcome of the research appears to be very efficient for generating fluctuation free electricity, power quality and reliability, energy saving/reutilization and system noise reduction.

Research of the test generation algorithm based on search state dominance for combinational circuit

On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation.

The structure-based multi-fault test generation algorithm for combinational circuit

In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%.

A new approach to test generation for combinational circuits

Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits （CC） based on the chaotic particle swarm optimization （CPSO） algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS＇ 85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected fauhs.with original test vector, and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective.

Optimal Stack Generation for CMOS Analog Modules with Parasitic and Mismatch Constraints

The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.Based on the proposed models,an optimal stack generation technique is developed to control the parasitics and mismatches,optimize the stack shape and ensure the generation of an Eulerian graph for a given CMOS analog module.An OPA circuit example is given to demonstrate that the circuit performances such as unit gain bandwidth and phase margin are enhanced by the proposed layout optimization method.

A Signal-Flow Driven Automatic Physical Synthesis Methodology for Analog Circuits

This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signal-flow,complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement,and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.

Multi-channel 28-GHz millimeter-wave signal generation on a silicon photonic chip with automated polarization control

We propose and experimentally demonstrate an integrated silicon photonic scheme to generate multi-channel millimeter-wave(MMW) signals for 5 G multi-user applications. The fabricated silicon photonic chip has a footprint of 1.1 × 2.1 mm^2 and integrates 7 independent channels each having on-chip polarization control and heterodyne mixing functions. 7 channels of4-Gb/s QPSK baseband signals are delivered via a 2-km multi-core fiber(MCF) and coupled into the chip with a local oscillator(LO) light. The polarization state of each signal light is automatically adjusted and aligned with that of the LO light, and then 7 channels of 28-GHz MMW carrying 4-Gb/s QPSK signals are generated by optical heterodyne beating. Automated polarizationcontrol function of each channel is also demonstrated with ～7-ms tuning time and ～27-dB extinction ratio.

PARAMETER DESIGN OF AN MHD PASSIVE POWER CONDITIONING CIRCUIT

This paper gives an equivalent circuit and a model of MHD generatorwith passive power conditioning circuit.The relative values of the current and voltagefluctuation on the load is obtained by means of simulation.The result can be used asa reference for designing a passive power conditioning circuit.

AN INVERTER SYSTEM FOR COAL-FIRED MHD GENERATOR

The paper introduces an inverter system designed for segmented diagonalMHD generator.The characteristics and composition of the MHD inverter is analysed.And its control structure and function are presented.

Test Generation and Design-for-Testability Based on Acyclic Structure with Hold Registers

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

Model Reduction by Generalized Falk Method for Efficient Dedicated to Professor Karl Stark Pister for his 95th birthday Field-Circuit Simulations

The Generalized Falk Method(GFM)for coordinate transformation,together with two model-reduction strategies based on this method,are presented for efficient coupled field-circuit simulations.Each model-reduction strategy is based on a decision to retain specific linearly-independent vectors,called trial vectors,to construct a vector basis for coordinate transformation.The reduced-order models are guaranteed to be stable and passive since the GFM is a congruence transformation of originally symmetric positive definite systems.We also show that,unlike the Pade-via-Lanczos(PVL)method,the GFM does not generate unstable positive poles while reducing the order´of circuit problems.Further,the proposed GFM is also faster when compared to methods of the type Lanczos(or Krylov)that are already widely used in circuit simulations for electrothermal and electromagnetic problems.The concept of response participation factors is introduced for the selection of the trial vectors in the proposed model-reduction methods.Further,we present methods to develop simple equivalent circuit networks for the field component of the overall field-circuit system.The implementation of these equivalent circuit networks in circuit simulators is discussed.With the proposed model-reduction strategies,significant improvement on the efficiency of the generalized Falk method is illustrated for coupled field-circuit problems.

A study on equivalent circuit model of lead-acid battery for electric vehicles

A 100Ah@42V lead-acid battery package for electric vehicles are used for study. 1he hybrid pulse test is applied to the battery package to acquire enough data, by which the partnership for a new generation of vehicles （PNGV） equivalent circuit model parameters are identified by the least square method. Then, the PNGV model is verified under two conditions, i.e., the composite pulse excitation and the constant-current respectively. The corresponding maximum relative errors of output voltage are less than 3 % and 3.5 %. Results show that the present PNGV equivalent circuit model and verification method is effective, which can satisfy requirement of simulation of power system of electric vehicles.

Impact of PV Distributed Generation on Loop Distribution Network

The rapid spreading of the Photovoltaic (PV) Systems as Distributed Generation (DG) in medium and low voltage networks created many effects and changes on the existing power system networks. In this work, two methods have been used and applied to determine the optimal allocation and sizing of the PV to be installed as DGs (ranging from 250 kW up to 3 MW). The first one is to determine the location according to the maximal power losses reduction over the feeder. The second one is by using the Harmony Search Algorithm which is claimed to be a powerful technique for optimal allocation of PV systems. The results of the two techniques were compared and found to be nearly closed. Furthermore, investigation on the effects on the feeder in terms of voltage levels, power factor readings, and short circuit current levels has been done. All calculations and simulations are conducted by using the MATLAB Simulation Program. Some field calculations and observations have been expended in order to substantiate the research findings and validation.

基于FPGA的m序列发生器设计与实验

如何设计出将m序列计算、FPGA和具体应用结合在一起的综合实验是数字逻辑电路、EDA等课程的重要内容。利用线性反馈移位寄存器设计了不同周期的m序列,给出了m序列的程序流程和仿真波形。采用FPGA生成m序列,并利用生成的m序列通过IGBT驱动,与光耦隔离电路、电源电路等组成扩频编码探地发射仪,该发射仪能确保在大范围之内收到地质信息,减少野外环境带来的干扰。该综合实验可以提高学生的学习兴趣,培养学生运用综合知识的能力。

合闸时间带电测量及自动准同期导前时间次最优整定的研究

本文提出了一种带电测量高压断路器合闸时间次的新方法及自动准同期导前时间最优整定的算法．利用本文提出的方法和算法，微机型快速准同期能够非常准确地捕捉到导前相角，以较小的冲击电流将发电机并入电网．

高频高压发生器维修案例分析

本文通过对高频高压发生器维修案例进行分析,论述了维修的方法和要点。

A Novel Island Detection Methodology for the Realization of Smart Grid

Responding to the problem of increased load demand, progress has been made to develop a new smarter infrastructure, which employs a decentralised approach. This smart decentralised system, termed smart grid, is composed of micro grids which utilise a combination of distributed energy resources (DER). The DERs can either be operated in parallel with the grid or in autonomous condition (intentional-islanding). Operating the DER under intentional islanding condition is seen as the next stage in smart grid’s future development which requires intelligent control implementation. In order to utilise this intelligent control, immediate detection of islanding is essential. This paper proposes a new smarter islanding detection method, which implements the forecast capability of smart grid by detecting the fluctuations before islanding occurs. The proposed method has been tested in simulation and compared against the current islanding detection methods. The simulation results have successfully proven the benefits of the new proposed method over the current methodologies in island detection.

A comparison study of on-chip short pulse generation circuits based on a coplanar waveguide

A few traditional pulse-forming circuits are implemented in a commercial 0.13 μm digital complementary-metal-oxide-semiconductor （CMOS） technology. These circuits, based on a coplanar waveguide, are analyzed and compared through CadenceTM Spectre simulations. The results show that these traditional pulse-forming-line （PFL） based circuits can be implemented in standard CMOS technology for short pulse generations. Further work is needed to explore the potential of the circuit techniques and to minimize parasitic effects.

Pseudo-Random Test Generation for Large Combinational Circuits

In this paper,a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing.Several interesting experimental results are obtained.It is found out that initial states of pseudo-random sequences have little effect on fault coverage.Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less than the number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as m decreases.The local unrandomness of pseudo-random sequences is exposed clearly.Generally,when an LFSR is employed as a pseudo-random generator,there are at least as many LFSR stages as circuit inputs.However,for large circuits under test with hundreds of inputs,there are drawbacks of using an LFSR with hundreds of stages.In the paper,a new design for a pseudo-random pattern generator is proposed in which m<n.The relationship between test length and the number of LFSR stages is discussed in order to obtain necessary,fault coverage.It is shown that the design cannot only save LFSR hardware but also reduce test length without loss of fault coverage,and is easy to implement. The experimental results are provided for the 10 Benchmark Circuits to show the effectiveness of the generator.

A Complete Critical Path Algorithm for Test Generation of Combinational Circuits

It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to make it a complete algorithm,we put forward a reconvergent-fanout- oriented technique,the principal critical path algorithm,propagating the critical value back to primary inputs along a single path,the principal critical path,and allowing multiple path sensitization if needed.Relationship among test patterns is also discussed to accelerate test generation.