VLSI testing is being pushed to the high-level based technology. In thispaper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The modelprovides a text format file, which is convenien...VLSI testing is being pushed to the high-level based technology. In thispaper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The modelprovides a text format file, which is convenient and more practical for developing succeedingRegister Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and soforth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL faultmodels and super faults defined, the concurrent fault simulation algorithm is given. Thecorresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments showthat the RTL fault simulator is efficient for VLSI circuits.展开更多
文摘VLSI testing is being pushed to the high-level based technology. In thispaper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The modelprovides a text format file, which is convenient and more practical for developing succeedingRegister Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and soforth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL faultmodels and super faults defined, the concurrent fault simulation algorithm is given. Thecorresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments showthat the RTL fault simulator is efficient for VLSI circuits.
