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A HW/SW Co-Verification Technique for FPGA Test 被引量:1
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作者 Yong-Bo Liao Ping Li Ai-Wu Ruan Yi-Wen Wang Wen-Chang Li 《Journal of Electronic Science and Technology of China》 2009年第4期390-394,共5页
Field programmable gate arrays (FPGAs) have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/soft... Field programmable gate arrays (FPGAs) have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software (HW/SW) co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block (IOB) and configurable logic block (CLB) of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work. 展开更多
关键词 configurable logic block field programmable gate array hardware/software co-verification input/output block.
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Novel Test Approach for Interconnect Resources in Field Programmable Gate Arrays
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作者 Yong-Bo Liao Wen-Chang Li Ping Li Ai-Wu Ruan 《Journal of Electronic Science and Technology》 CAS 2011年第1期85-89,共5页
A novel test approach for interconnect resources (IRs) in field programmable gate arrays (FPGA) has been proposed.In the test approach,SBs (switch boxes) of IRs in FPGA has been utilized to test IRs.Furthermore,... A novel test approach for interconnect resources (IRs) in field programmable gate arrays (FPGA) has been proposed.In the test approach,SBs (switch boxes) of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks (CLBs) in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip (SoC) hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns. 展开更多
关键词 configurable logic blocks configuretion pattern field programmable gate arrays interconnect resources test switch box.
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A new FPGA with 4/5-input LUT and optimized carry chain
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作者 毛志东 陈利光 +1 位作者 王元 来金梅 《Journal of Semiconductors》 EI CAS CSCD 2012年第7期113-120,共8页
A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their ne... A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources. We also develop a new carry chain structure with an optimized critical path. Finally a newly designed configurable scan-chain is inserted. The circuit is fabricated in 0.13μm 1P8M 1.2/2.5/3.3 V logic CMOS process. The test results show a correct function of 4/5-input LUT and scan- chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 72.5%. Our results also show that the logic utilization of this work is better than that of a Virtex lI/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex lI/Virtex 4 FPGA when implemented using only 5-LUT. 展开更多
关键词 FPGA configurable logic block 4/5-input LUT carry chain optimization scan-chain
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