On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method

The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.

An Ultra-Low Specific On-Resistance VDMOS with a Step Oxide-Bypassed Trench Structure

A novel Step Oxide-Bypassed （SOB） trench VDMOS structure is designed based on the Oxide-Bypassed concept proposed by Liang Y C. This structure is suitable for breakdown voltage below 300V to obtain ultra-low specific on-resistance. The main feature of this structure is the various thicknesses of sidewall oxide,which modulate electric field distribution in the drift region and the charge compensation effect. As a result, the breakdown voltage is increased no less than 20% due to the more uniform electric field of the drift region,while the specific on-resistance was reduced by 40%-60% for the step oxide bypassed compared with the oxide-bypassed structure.

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

Low specific on-resistance GaN-based vertical heterostructure field effect transistors with nonuniform doping superjunctions

A novel Ga N-based vertical heterostructure field effect transistor（HFET） with nonuniform doping superjunctions（non-SJ HFET） is proposed and studied by Silvaco-ATLAS,for minimizing the specific on-resistance（RonA） at no expense of breakdown voltage（BV）.The feature of non-SJ HFET lies in the nonuniform doping concentration from top to bottom in the n-and p-pillars,which is different from that of the conventional Ga N-based vertical HFET with uniform doping superjunctions（un-SJ HFET）.A physically intrinsic mechanism for the nonuniform doping superjunction（non-SJ） to further reduce RonA at no expense of BV is investigated and revealed in detail.The design,related to the structure parameters of non-SJ,is optimized to minimize the RonA on the basis of the same BV as that of un-SJ HFET.Optimized simulation results show that the reduction in RonA depends on the doping concentrations and thickness values of the light and heavy doping parts in non-SJ.The maximum reduction of more than 51% in RonA could be achieved with a BV of 1890 V.These results could demonstrate the superiority of non-SJ HFET in minimizing RonA and provide a useful reference for further developing the Ga N-based vertical HFETs.

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high-κ insulator

An improved vertical power double-diffused metal–oxide–semiconductor（DMOS） device with a p-region（P1） and high-κ insulator vertical double-diffusion metal–oxide–semiconductor（HKP-VDMOS） is proposed to achieve a better performance on breakdown voltage（BV）/specific on-resistance（Ron,sp） than conventional VDMOS with a high-κ insulator（CHK-VDMOS）.The main mechanism is that with the introduction of the P-region,an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage.Due to the assisted depletion effect of this p-region,the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region.Meanwhile,based on the superposition of the depleted charges,a closed-form model for electric field/breakdown voltage is generally derived,which is in good agreement with the simulation result within 10% of error.An HKP-VDMOS device with a breakdown voltage of 600 V,a reduced specific on-resistance of 11.5 Ωm·cm^2 and a figure of merit（FOM）（BV^2/Ron,sp）of 31.2 MW·cm^-2 shows a substantial improvement compared with the CHK-VDMOS device.

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

A new ultra-low specific on-resistance （Ron,sp） vertical double diffusion metal-oxide-semiconductor field-effect tran- sistor （VDMOS） with continuous electron accumulation （CEA） layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration （Am）. In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp. Especially, the two PNjunctions within the trench gate support a high gate--drain voltage in the off-state and on-state, re- spectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS （CSJ-VDMOS） at the same high breakdown voltage （BV）.

Low on-resistance 1.2 kV 4H-SiC power MOSFET with Ron, sp of 3.4 mΩ·cm^2

A 4H-SiC power MOSFET with specific on-resistance of 3.4 mΩ·cm^2 and breakdown voltage exceeding 1.5 kV is designed and fabricated.Numerical simulations are carried out to optimize the electric field strength in gate oxide and at the surface of the semiconductor material in the edge termination region.Additional n-type implantation in JFET region is implemented to reduce the specific on-resistance.The typical leakage current is less than 1μA at VDS=1.4 kV.Drain–source current reaches 50 A at VDS=0.75 V and VGS=20 V corresponding to an on-resistance of 15 mΩ.The typical gate threshold voltage is 2.6 V.

Novel high- with low specific on-resistance high voltage lateral double-diffused MOSFET

A novel voltage-withstand substrate with high-K（HK, k 〉 3.9, k is the relative permittivity） dielectric and low specific on-resistance（Ron,sp） bulk-silicon, high-voltage LDMOS（HKLR LDMOS）is proposed in this paper. The high-K dielectric and highly doped interface N＋-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration（Nd） and reshape the electric field distribution. The highly doped N＋-layer under the high-K dielectric acts as a low resistance path to reduce the Ron,sp. The new device with the high breakdown voltage（BV）, the low Ron,sp, and the excellent figure of merit（FOM = BV^2/Ron,sp） is obtained. The BV of HKLR LDMOS is 534 V, Ron,sp is 70.6 m？·cm^2, and FOM is 4.039 MW·cm^（-2）.

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance（Ron,sp） integrable silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer（BOX）（DGRD MOSFET）.First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage（BV）.The BV of 233 V and Ron,sp of 4.151 mΩ·cm2（VGS = 15 V） are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.

Granular behaviour under bi-directional shear with constant vertical stress and constant volume

This paper aims to investigate the role of bi-directional shear in the mechanical behaviour of granular materials and macro-micro relations by conducting experiments and discrete element method(DEM)modelling.The bi-directional shear consists of a static shear consolidation and subsequent shear under constant vertical stress and constant volume conditions.A side wall node loading method is used to exert bi-directional shear of various angles.The results show that bi-directional shear can significantly influence the mechanical behaviour of granular materials.However,the relationship between bidirectional shear and mechanical responses relies on loading conditions,i.e.constant vertical stress or constant volume conditions.The stress states induced by static shear consolidation are affected by loading angles,which are enlarged by subsequent shear,consistent with the relationship between bidirectional shear and principal stresses.It provides evidence for the dissipation of stresses accompanying static liquefaction of granular materials.The presence of bi-directional principal stress rotation(PSR)is demonstrated,which evidences why the bi-directional shear of loading angles with components in two directions results in faster dissipations of stresses with static liquefaction.Contant volume shearing leads to cross-anisotropic stress and fabric at micro-contacts,but constant vertical stress shearing leads to complete anisotropic stress and fabric at micro-contacts.It explains the differentiating relationship between stress-strain responses and fabric anisotropy under these two conditions.Micromechanical signatures such as the slip state of micro-contacts and coordination number are also examined,providing further insights into understanding granular behaviour under bi-directional shear.

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

An ultra-low specific on-resistance （Ron,sp） oxide trench-type silicon-on-insulator （SOI） lateral double-diffusion metal-oxide semiconductor （LDMOS） with an enhanced breakdown voltage （BV） is proposed and investigated by simulation. There are two key features in the proposed device： one is a U-shaped gate around the oxide trench, which extends from source to drain （UG LDMOS）; the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field （E-field） strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron,sp of 12.4 mΩ.cm2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS （CT LDMOS）, realizing the state-of-the-art trade-off between BV and Ron,sp.

Ultralow Specific on-Resistance Trench MOSFET with a U-Shaped Extended Gate

An ultralow specific on-resistance （Ron,sp） trench metal-oxide-semiconductor field effect transistor （MOSFET） with an improved off-state breakdown voltage （BV） is proposed. It features a U-shaped gate around the drift region and an oxide trench inserted in the drift region （UG MOSFET）. In the on-state, the U-shaped gate induces a high density electron accumulation layer along its sidewall, which provides a low-resistance current path from the source to the drain, realizing an ultralow Ron,sp. The value of Ron,sp is almost independent of the drift doping concentration, and thus the UG MOSFET breaks through the contradiction relationship between R p and the off-state BV. Moreover, the oxide trench folds the drift region, enabling the UG MOSFET to support a high BV with a shortened cell pitch. The UG MOSFET achieves an Ron,sp of 2 mΩ·cm^2 and an improved BV of 216 V, superior to the best existing state-of-the-art transistors at the same BV level

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance

A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.

ESTIMATE ON THE BLOCH CONSTANT FOR CERTAIN HARMONIC MAPPINGS UNDER A DIFFERENTIAL OPERATOR

In this paper,we first obtain the precise values of the univalent radius and the Bloch constant for harmonic mappings of the formL(f)=zfz-zfz,where f represents normalized harmonic mappings with bounded dilation.Then,using these results,we present better estimations for the Bloch constants of certain harmonic mappings L(f),where f is a K-quasiregular harmonic or open harmonic.Finally,we establish three versions of BlochLandau type theorem for biharmonic mappings of the form L(f).These results are sharp in some given cases and improve the related results of earlier authors.

Cyclic shear behavior of en-echelon joints under constant normal stiffness conditions

To reveal the mechanism of shear failure of en-echelon joints under cyclic loading,such as during earthquakes,we conducted a series of cyclic shear tests of en-echelon joints under constant normal stiffness(CNS)conditions.We analyzed the evolution of shear stress,normal stress,stress path,dilatancy characteristics,and friction coefficient and revealed the failure mechanisms of en-echelon joints at different angles.The results show that the cyclic shear behavior of the en-echelon joints is closely related to the joint angle,with the shear strength at a positive angle exceeding that at a negative angle during shear cycles.As the number of cycles increases,the shear strength decreases rapidly,and the difference between the varying angles gradually decreases.Dilation occurs in the early shear cycles(1 and 2),while contraction is the main feature in later cycles(310).The friction coefficient decreases with the number of cycles and exhibits a more significant sensitivity to joint angles than shear cycles.The joint angle determines the asperities on the rupture surfaces and the block size,and thus determines the subsequent shear failure mode(block crushing and asperity degradation).At positive angles,block size is more greater and asperities on the rupture surface are smaller than at nonpositive angles.Therefore,the cyclic shear behavior is controlled by block crushing at positive angles and asperity degradation at negative angles.

Gedankenexperiment for Modified ZPE and Planck’s “Constant”, h, in the Beginning of Cosmological Expansion, Partly Due to NLED

We initially look at a non singular universe representation of entropy, based in part on what was brought up by Muller and Lousto. This is a gateway to bringing up information and computational steps (as defined by Seth Lloyd) as to what would be available initially due to a modified ZPE formalism. The ZPE formalism is modified as due to Matt Visser’s alternation of k (maximum) ~ 1/(Planck length), with a specific initial density giving rise to initial information content which may permit fixing the initial Planck’s constant, h, which is pivotal to the setting of physical law. The settings of these parameters depend upon NLED.

Elementary Fermions: Strings, Planck Constant, Preons and Hypergluons

Using real fields instead of complex ones, it is suggested here that the fermions are pairs of coupled strings with an internal tension. The interaction between the two coupled strings is due to an exchange mechanism which is proportional to Planck’s constant. This may be the result of two massless bosons (hypergluons) coupled by a preon (prequark) exchange. It also gives a physical explanation to the origin of the Planck constant, and origin of spin.