This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a thi...This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.展开更多
An approach to identification of linear continuous-time system is studied with modulating functions. Based on wavelet analysis theory, the multi-resolution modulating functions are designed, and the corresponding filt...An approach to identification of linear continuous-time system is studied with modulating functions. Based on wavelet analysis theory, the multi-resolution modulating functions are designed, and the corresponding filters have been analyzed. Using linear modulating filters, we can obtain an identification model that is parameterized directly in continuous-time model parameters. By applying the results from discrete-time model identification to the obtained identification model, a continuous-time estimation method is developed. Considering the accuracy of parameter estimates, an instrumental variable (Ⅳ) method is proposed, and the design of modulating integral filter is discussed. The relationship between the accuracy of identification and the parameter of modulating filter is investigated, and some points about designing Gaussian wavelet modulating function are outlined. Finally, a simulation study is also included to verify the theoretical results.展开更多
An efficient unbiased estimation method is proposed for the direct identification of linear continuous-time system with noisy input and output measurements.Using the Gaussian modulating filters,by numerical integratio...An efficient unbiased estimation method is proposed for the direct identification of linear continuous-time system with noisy input and output measurements.Using the Gaussian modulating filters,by numerical integration,an equivalent discrete identification model which is parameterized with continuous-time model parameters is developed,and the parameters can be estimated by the least-squares (LS) algorithm.Even with white noises in input and output measurement data,the LS estimate is biased,and the bias is determined by the variances of noises.According to the asymptotic analysis,the relationship between bias and noise variances is derived.One equation relating to the measurement noise variances is derived through the analysis of the LS errors.Increasing the degree of denominator of the system transfer function by one,an extended model is constructed.By comparing the true value and LS estimates of the parameters between original and extended model,another equation with input and output noise variances is formulated.So,the noise variances are resolved by the set of equations,the LS bias is eliminated and the unbiased estimates of system parameters are obtained.A simulation example by comparing the standard LS with bias eliminating LS algorithm indicates that the proposed algorithm is an efficient method with noisy input and output measurements.展开更多
In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modu...In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.展开更多
This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-...This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.展开更多
A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits i...A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.展开更多
A 1-V third order one-bit continuous-time(CT) EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficien...A 1-V third order one-bit continuous-time(CT) EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.展开更多
A continuous-time ∑△ modulator with a third-order loop filter and a 3-bit quantizer is realized. The modulator is robust to the excess loop delay, clock jitter, and RC product variations. When designing the integra...A continuous-time ∑△ modulator with a third-order loop filter and a 3-bit quantizer is realized. The modulator is robust to the excess loop delay, clock jitter, and RC product variations. When designing the integrator, an op-amp with novel GBW extension structure, improving the linearity of the loop filter, is adopted. The prototype chip is designed in a 130 nm CMOS technology, targeting FM radio applications. The experimental results show that the prototype modulator achieves a 72 dB dynamic range and a 70.7 dB signal to noise and distortion ratio over a 500 kHz bandwidth with a 26 MHz clock, consuming 2.52 mW power from a 1.2 V supply.展开更多
For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor (SC) sigma-delta modulator (SDM) is proposed. Based on the principle and...For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor (SC) sigma-delta modulator (SDM) is proposed. Based on the principle and the topology structure of the SDMs, the influence of oversampling ratio, bits of an internal quantizer and the cascaded structure on weak signal detecting precision is analyzed, and an ideal low-distortion SDM with a second-order 1-bit structure satisfying the high- resolution interface circuit of an accelerometer is designed. With the research on non-idealities of each SDM block in the SC circuit implementation and their impacts on power consumption, the realized parameters of low-power SDMs based on different bandwidths are devised and the power consumption of each SDM is estimated. Time-domain behavioral simulation is explored based on Simulink. The results demonstrate that a 21- bit resolution of the designed SDMs can be achieved on the premise of low power, and the parameters for the circuit implementation can be directed to the transistor-level circuit design.展开更多
A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector(PFD),a maximum re...A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector(PFD),a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.展开更多
A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilizat...A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilization is applied to the first integrator to eliminate the 1/f noise.A low-power,area-efficient decimator is used,which includes a poly-phase comb-filter and a wave-digital-filter.The converter achieves a 92dB dynamic range over the 96kHz audio band.This single chip occupies 2.68mm2 in a 0.18μm six-metal CMOS process and dissipates only 15.5mW power.展开更多
A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-...A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.展开更多
This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in ...This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.展开更多
To improve the simulation accuracy of SIMULINK, a novel inclusive behavior model of an integrator is proposed that introduces the effects of different circuit nonidealities of a switched-capacitor sigma-delta modulato...To improve the simulation accuracy of SIMULINK, a novel inclusive behavior model of an integrator is proposed that introduces the effects of different circuit nonidealities of a switched-capacitor sigma-delta modulator into SIMULIK simulation. The nonlinear DC gain and nonlinear settling process are introduced into the op-amp module. The signaldependent charge injection and nonlinear resistance are introduced into the switch module. In addition, the noise source including flicker and thermal noise is introduced into system as an independent module. The novel model is verified by SIMULINK behavioral simulations. The results are compared with results from circuit level simulation in Cadence SPICE using TSMC 0.35μm mixed signal technology. It shows that the novel model succeeds in introducing the influences of the nonidealities into behavior simulation to more realistically describe the circuit performances and increase the accuracy of SIMULINK simulation.展开更多
A fourth-order switched-capacitor bandpass ∑△ modulator is presented for digital intermediatefrequency (IF) receivers. The circuit operates at a sampling frequency of 100 MHz. The transfer function of the resonato...A fourth-order switched-capacitor bandpass ∑△ modulator is presented for digital intermediatefrequency (IF) receivers. The circuit operates at a sampling frequency of 100 MHz. The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators. The modulator is implemented in a 0.13-μm standard CMOS process. The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB, respectively, over a bandwidth of 200 kHz centered at 25 MHz, and the power dissipation is 8.2 mW at a 1.2 V supply.展开更多
Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and d...Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.展开更多
This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audioband sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the ch...This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audioband sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the challenges associated with continuous-time design. Measurement results show that the peak SNR of this ADC reaches 100 dB and the total power consumption is less than 30 mW.展开更多
Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode(DCM) c...Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode(DCM) controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.展开更多
An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its su...An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier's stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier's noise performance is also presented.展开更多
文摘This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.
基金This project was supported by China Postdoctoral Science Foundation (2003034466)Scientific Research Fund of Hunan Provincial Education Department (02B032).
文摘An approach to identification of linear continuous-time system is studied with modulating functions. Based on wavelet analysis theory, the multi-resolution modulating functions are designed, and the corresponding filters have been analyzed. Using linear modulating filters, we can obtain an identification model that is parameterized directly in continuous-time model parameters. By applying the results from discrete-time model identification to the obtained identification model, a continuous-time estimation method is developed. Considering the accuracy of parameter estimates, an instrumental variable (Ⅳ) method is proposed, and the design of modulating integral filter is discussed. The relationship between the accuracy of identification and the parameter of modulating filter is investigated, and some points about designing Gaussian wavelet modulating function are outlined. Finally, a simulation study is also included to verify the theoretical results.
基金Project(50875028) supported by the National Natural Science Foundation of China
文摘An efficient unbiased estimation method is proposed for the direct identification of linear continuous-time system with noisy input and output measurements.Using the Gaussian modulating filters,by numerical integration,an equivalent discrete identification model which is parameterized with continuous-time model parameters is developed,and the parameters can be estimated by the least-squares (LS) algorithm.Even with white noises in input and output measurement data,the LS estimate is biased,and the bias is determined by the variances of noises.According to the asymptotic analysis,the relationship between bias and noise variances is derived.One equation relating to the measurement noise variances is derived through the analysis of the LS errors.Increasing the degree of denominator of the system transfer function by one,an extended model is constructed.By comparing the true value and LS estimates of the parameters between original and extended model,another equation with input and output noise variances is formulated.So,the noise variances are resolved by the set of equations,the LS bias is eliminated and the unbiased estimates of system parameters are obtained.A simulation example by comparing the standard LS with bias eliminating LS algorithm indicates that the proposed algorithm is an efficient method with noisy input and output measurements.
基金Sponsored by the National Basic Research Program of China(Grant No.2012CB934104)
文摘In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.
基金the National Natural Science Foundation of China (No. 60025101, No.90207001, and No. 90307016).
文摘This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.
文摘A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.
基金supported by the National High Technology Research and Development Program of China(No.2008AA010702)
文摘A 1-V third order one-bit continuous-time(CT) EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.
文摘A continuous-time ∑△ modulator with a third-order loop filter and a 3-bit quantizer is realized. The modulator is robust to the excess loop delay, clock jitter, and RC product variations. When designing the integrator, an op-amp with novel GBW extension structure, improving the linearity of the loop filter, is adopted. The prototype chip is designed in a 130 nm CMOS technology, targeting FM radio applications. The experimental results show that the prototype modulator achieves a 72 dB dynamic range and a 70.7 dB signal to noise and distortion ratio over a 500 kHz bandwidth with a 26 MHz clock, consuming 2.52 mW power from a 1.2 V supply.
基金The National High Technology Research and Development Program of China (863 Program) ( No. 2006AA12Z302)
文摘For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor (SC) sigma-delta modulator (SDM) is proposed. Based on the principle and the topology structure of the SDMs, the influence of oversampling ratio, bits of an internal quantizer and the cascaded structure on weak signal detecting precision is analyzed, and an ideal low-distortion SDM with a second-order 1-bit structure satisfying the high- resolution interface circuit of an accelerometer is designed. With the research on non-idealities of each SDM block in the SC circuit implementation and their impacts on power consumption, the realized parameters of low-power SDMs based on different bandwidths are devised and the power consumption of each SDM is estimated. Time-domain behavioral simulation is explored based on Simulink. The results demonstrate that a 21- bit resolution of the designed SDMs can be achieved on the premise of low power, and the parameters for the circuit implementation can be directed to the transistor-level circuit design.
文摘A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector(PFD),a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.
文摘A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilization is applied to the first integrator to eliminate the 1/f noise.A low-power,area-efficient decimator is used,which includes a poly-phase comb-filter and a wave-digital-filter.The converter achieves a 92dB dynamic range over the 96kHz audio band.This single chip occupies 2.68mm2 in a 0.18μm six-metal CMOS process and dissipates only 15.5mW power.
基金Project Supported by the Important National Science & Technology Specific Projects of China(No.2009ZXO1O31-003-002)the State Key Laboratory Project of China(No.11MS002)
文摘A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.
文摘This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.
基金the National Natural Science Foundation of China(No.90707002)~~
文摘To improve the simulation accuracy of SIMULINK, a novel inclusive behavior model of an integrator is proposed that introduces the effects of different circuit nonidealities of a switched-capacitor sigma-delta modulator into SIMULIK simulation. The nonlinear DC gain and nonlinear settling process are introduced into the op-amp module. The signaldependent charge injection and nonlinear resistance are introduced into the switch module. In addition, the noise source including flicker and thermal noise is introduced into system as an independent module. The novel model is verified by SIMULINK behavioral simulations. The results are compared with results from circuit level simulation in Cadence SPICE using TSMC 0.35μm mixed signal technology. It shows that the novel model succeeds in introducing the influences of the nonidealities into behavior simulation to more realistically describe the circuit performances and increase the accuracy of SIMULINK simulation.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011600)the Young Scientists Fund of Fudan University,China(No.09FQ33)the State Key Laboratory ASIC & System of Fudan University,China(No. 09MS008)
文摘A fourth-order switched-capacitor bandpass ∑△ modulator is presented for digital intermediatefrequency (IF) receivers. The circuit operates at a sampling frequency of 100 MHz. The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators. The modulator is implemented in a 0.13-μm standard CMOS process. The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB, respectively, over a bandwidth of 200 kHz centered at 25 MHz, and the power dissipation is 8.2 mW at a 1.2 V supply.
基金Project supported by the National Science Fund for Distinguished Young Scholars of China(No.60925015)
文摘Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.
文摘This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audioband sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the challenges associated with continuous-time design. Measurement results show that the peak SNR of this ADC reaches 100 dB and the total power consumption is less than 30 mW.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011607)
文摘Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode(DCM) controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.
基金supported by the National Natural Science Foundation of China(No.60576028)
文摘An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier's stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier's noise performance is also presented.