Unified Coverage Methodology for SoC Post-Silicon Validation

The System-on-Chip’s increased complexity and shortened design cycle calls for innovation in design and validation. A high quality System-on-Chip creates distinction and position in the market, and validation is the key to a quality product. Validation consumes >60% of the product cycle. Therefore, validation should be carried out efficiently. Validation must be quantified to aid in determining its quality. Pre-silicon uses various coverage metrics for quantifying the validation. The available on-chip coverage logic limits the use of pre-silicon-like coverage metrics in post-silicon. Although on-chip coverage logic increases observability, it does not contribute to the functional logic;hence, they are controlled and limited. Discounting the need for the on-chip coverage logic, the question to be answered is whether or not these pre-silic-on coverage metrics applicable to post-silicon. We discuss the reasons for limited applicability of pre-silicon coverage metrics in post-silicon. This paper presents a unified SoC post-silicon coverage methodology centered on functional coverage metrics.

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage

Coverage evaluation is indispensable for verification via simulation. As the functional complexity of modern design is increasing at a breathtaking pace, it is requisite to take observability into account. Unfortunately, nowadays coverage metrics taking observability into account are not very satisfactory. On the one hand, for the observability assessment algorithms proposed up to now, the overhead of computing is large, so they could not be integrated into simulation tools easily. On the other hand, the vector generation methods involving the metrics taking observability into account are not very efficient, and there exists a disconnection between these metrics and the vector generation process. In this paper, some original ideas for the problems above are presented. （1） Precise and concise abstract representations from HDL （Hardware Description Language） descriptions at RTL （Register Transfer Level） are presented to model observability information. （2） A novel observability evaluation method based on the proposed models is introduced. This method is more computationally efficient than prior efforts to assess observability and it could be integrated into compilers and simulators easily. （3） A new simulation vector generation procedure involving the observability-enhanced statement coverage metric is developed. The method is simulation：based and driven by the distribution of unobserved statements. During this procedure, the proposed algorithm always tries to cover all unobserved statements, and reduce unnecessary backtracking, so it is efficient. The methods proposed have been implemented as a prototype tool for VHDL designs, and the results on benchmarks show significant benefits.