针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,...针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。展开更多
In conventional cross-coupled controller design,the method usually ignored the inherent characteristic of time-vary- ing parameters and model uncertainties in system.In this paper,a cross-coupled controller(CCC)using ...In conventional cross-coupled controller design,the method usually ignored the inherent characteristic of time-vary- ing parameters and model uncertainties in system.In this paper,a cross-coupled controller(CCC)using an H~∞control scheme has been proposed to reduce the contouring error for an X-Y table.Furthermore,the proposed CCC design,which is a typical Multi- Input Multi-Output(MIMO)system with linear time varying(LTV)characteristics,has been verified as being internally stable. The simulations are carried on Matlab simulink to verify the proposed method,and the results showed that the proposed method can reduce the contouring error significantly compared with the conventional one.展开更多
By analyzing the principle of process variations, a lightweight Physical Unclonable Function(PUF) circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled invert...By analyzing the principle of process variations, a lightweight Physical Unclonable Function(PUF) circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation(SMIC) 65 nm CMOS technology and the layout area is 2.94 mm × 1.68 mm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.展开更多
This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4...This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4×subharmonic mixers. It would be impossible to avoid the presence of harmonics in CMOS VCO circuits. These harmonics are in general, undesirable signals which tend to accompany the desired fundamental signal. There are common-mode nodes (similar to those in the two source nodes in a cross-coupled VCO) in deferential VCO at which higher-order harmonics are present while the fundamental is absent in essence. We can make use of these second-order harmonics which are present at the common-mode nodes of two VCO in order to implement a quadrature connection between the fundamental outputs. The technique through which this is done is called superharmonic coupling. This CMOS quadrature VCO which applies active superharmonic coupling puts an excellent performance in show, with an output power –0.942 dBm for fundamental and –9.751 dBm for subharmonic, phase noise –107.2 dBc/Hz for fundamental and –114.8 dBc/Hz at a 1MHz offset. All of circuit applied are designed and simulated by ADS, 2008.展开更多
With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Curren...With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.展开更多
文摘针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。
文摘In conventional cross-coupled controller design,the method usually ignored the inherent characteristic of time-vary- ing parameters and model uncertainties in system.In this paper,a cross-coupled controller(CCC)using an H~∞control scheme has been proposed to reduce the contouring error for an X-Y table.Furthermore,the proposed CCC design,which is a typical Multi- Input Multi-Output(MIMO)system with linear time varying(LTV)characteristics,has been verified as being internally stable. The simulations are carried on Matlab simulink to verify the proposed method,and the results showed that the proposed method can reduce the contouring error significantly compared with the conventional one.
基金Supported by the National Natural Science Foundation of China(Nos.61474068,61404076,61274132)the Zhejiang Provincial Natural Science Foundation of China(No.LQ14F040001)the Doctoral Program of Higher Education of China(No.20113305110005)
文摘By analyzing the principle of process variations, a lightweight Physical Unclonable Function(PUF) circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation(SMIC) 65 nm CMOS technology and the layout area is 2.94 mm × 1.68 mm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.
文摘This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4×subharmonic mixers. It would be impossible to avoid the presence of harmonics in CMOS VCO circuits. These harmonics are in general, undesirable signals which tend to accompany the desired fundamental signal. There are common-mode nodes (similar to those in the two source nodes in a cross-coupled VCO) in deferential VCO at which higher-order harmonics are present while the fundamental is absent in essence. We can make use of these second-order harmonics which are present at the common-mode nodes of two VCO in order to implement a quadrature connection between the fundamental outputs. The technique through which this is done is called superharmonic coupling. This CMOS quadrature VCO which applies active superharmonic coupling puts an excellent performance in show, with an output power –0.942 dBm for fundamental and –9.751 dBm for subharmonic, phase noise –107.2 dBc/Hz for fundamental and –114.8 dBc/Hz at a 1MHz offset. All of circuit applied are designed and simulated by ADS, 2008.
基金The Open Project Program of the Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems(2023SZKF17)the University Synergy Innovation Program of Anhui Province(GXXT-2022-080)。
文摘With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.
